upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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554 lines
21 KiB
554 lines
21 KiB
/*
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* (C) Copyright 2007-2008
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* Larry Johnson, lrj@acm.org
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*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* korat.h - configuration for Korat board
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*
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* Manufacturer's information serial EEPROM parameters
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*/
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#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
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#define MAN_INFO_FIELD 2
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#define MAN_INFO_LENGTH 9
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#define MAN_MAC_ADDR_FIELD 3
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#define MAN_MAC_ADDR_LENGTH 12
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/*
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* Base addresses -- Note these are effective addresses where the actual
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* resources get mapped (not physical addresses).
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*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH0_SIZE 0x01000000
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#define CFG_FLASH0_ADDR (-CFG_FLASH0_SIZE)
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#define CFG_FLASH1_TOP 0xF8000000
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#define CFG_FLASH1_MAX_SIZE 0x08000000
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#define CFG_FLASH1_ADDR (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
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#define CFG_FLASH_BASE CFG_FLASH1_ADDR /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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/* Don't change either of these */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_USB2D0_BASE 0xe0000100
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#define CFG_USB_DEVICE 0xe0000000
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#define CFG_USB_HOST 0xe0000400
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#define CFG_CPLD_BASE 0xc0000000
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/*
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* Initial RAM & stack pointer
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*/
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/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
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#undef CFG_INIT_RAM_DCACHE
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*
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* Serial Port
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*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
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/*
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* FLASH related
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*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CFG_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/*
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* DDR SDRAM
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*/
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#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define SPD_EEPROM_ADDRESS {0x50}
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#define CONFIG_PROG_SDRAM_TLB
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#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C RTC */
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#define CONFIG_RTC_M41T60 1
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#define CFG_I2C_RTC_ADDR 0x68
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/* I2C SYSMON (LM73) */
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#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
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#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_MIN_TEMP -30
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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/* Setup some board specific values for the default environment variables */
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#define CONFIG_HOSTNAME korat
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#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
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#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
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/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CFG_BOOTFILE \
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CFG_ROOTPATH \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"kernel_addr=F4000000\0" \
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"ramdisk_addr=F4400000\0" \
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"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
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"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
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"cp.b 200000 FFFA0000 60000\0" \
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"upd=run load update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
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#define CONFIG_PHY_DYNAMIC_ANEG 1
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#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
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/* buffers & descriptors */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 3
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* Comment this out to enable USB 1.1 device */
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#define USB_2_0_DEVICE
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_SUBNETMASK
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_I2C_CMD_TREE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_USB
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ECC | \
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CFG_POST_ETHER | \
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CFG_POST_FPU | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_LOGBUFFER
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#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#define CONFIG_SUPPORT_VFAT
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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/* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*
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* Korat-specific options
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*/
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#define CFG_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
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/*
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* PCI stuff
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
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/* CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data have to be in the
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* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
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* during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#if CFG_FLASH0_SIZE == 0x01000000
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#define CFG_EBC_PB0AP 0x04017300
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#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x0009A000)
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#elif CFG_FLASH0_SIZE == 0x04000000
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#define CFG_EBC_PB0AP 0x04017300
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#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x000DA000)
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#else
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#error Unable to configure chip select for current CFG_FLASH0_SIZE
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#endif
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/* Memory Bank 1 (NOR-FLASH) initialization */
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#if CFG_FLASH1_MAX_SIZE == 0x08000000
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#define CFG_EBC_PB1AP 0x04017300
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#define CFG_EBC_PB1CR (CFG_FLASH1_ADDR | 0x000FA000)
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#else
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#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
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#endif
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/* Memory Bank 2 (CPLD) initialization */
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#define CFG_EBC_PB2AP 0x04017300
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#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
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/*
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* GPIO Setup
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*
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* Korat GPIO usage:
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*
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* Init.
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* Pin Source I/O value Function
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* ------ ------ --- ----- ---------------------------------
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* GPIO00 Alt1 I/O x PerAddr07
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* GPIO01 Alt1 I/O x PerAddr06
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* GPIO02 Alt1 I/O x PerAddr05
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* GPIO03 GPIO x x GPIO03 to expansion bus connector
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* GPIO04 GPIO x x GPIO04 to expansion bus connector
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* GPIO05 GPIO x x GPIO05 to expansion bus connector
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* GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
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* GPIO07 Alt1 O x PerCS2 (CPLD)
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* GPIO08 Alt1 O x PerCS3 to expansion bus connector
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* GPIO09 Alt1 O x PerCS4 to expansion bus connector
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* GPIO10 Alt1 O x PerCS5 to expansion bus connector
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* GPIO11 Alt1 I x PerErr
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* GPIO12 GPIO O 0 ATMega !Reset
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* GPIO13 GPIO O 1 SPI Atmega !SS
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* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
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* GPIO15 GPIO O 0 CPU Run LED !On
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* GPIO16 Alt1 O x GMC1TxD0
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* GPIO17 Alt1 O x GMC1TxD1
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* GPIO18 Alt1 O x GMC1TxD2
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* GPIO19 Alt1 O x GMC1TxD3
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* GPIO20 Alt1 I x RejectPkt0
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* GPIO21 Alt1 I x RejectPkt1
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* GPIO22 GPIO I x PGOOD_DDR
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* GPIO23 Alt1 O x SCPD0
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* GPIO24 Alt1 O x GMC0TxD2
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* GPIO25 Alt1 O x GMC0TxD3
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* GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
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* GPIO27 GPIO O 0 PHY #0 1000BASE-X select
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* GPIO28 GPIO O 0 PHY #1 1000BASE-X select
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* GPIO29 GPIO I x Test jumper !Present
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* GPIO30 GPIO I x SFP module #0 !Present
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* GPIO31 GPIO I x SFP module #1 !Present
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*
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* GPIO32 GPIO O 1 SFP module #0 Tx !Enable
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* GPIO33 GPIO O 1 SFP module #1 Tx !Enable
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* GPIO34 Alt2 I x !UART1_CTS
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* GPIO35 Alt2 O x !UART1_RTS
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* GPIO36 Alt1 I x !UART0_CTS
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* GPIO37 Alt1 O x !UART0_RTS
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* GPIO38 Alt2 O x UART1_Tx
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* GPIO39 Alt2 I x UART1_Rx
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* GPIO40 Alt1 I x IRQ0 (Ethernet 0)
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* GPIO41 Alt1 I x IRQ1 (Ethernet 1)
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* GPIO42 Alt1 I x IRQ2 (PCI interrupt)
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* GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
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* GPIO44 xxxx x x (grounded through pulldown)
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* GPIO45 GPIO O 0 PHY #0 Enable
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* GPIO46 GPIO O 0 PHY #1 Enable
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* GPIO47 GPIO I x Reset switch !Pressed
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* GPIO48 GPIO I x Shutdown switch !Pressed
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* GPIO49 xxxx x x (reserved for trace port)
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* . . . . .
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* . . . . .
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* . . . . .
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* GPIO63 xxxx x x (reserved for trace port)
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*/
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#define CFG_GPIO_ATMEGA_RESET_ 12
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#define CFG_GPIO_ATMEGA_SS_ 13
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#define CFG_GPIO_PHY0_FIBER_SEL 27
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#define CFG_GPIO_PHY1_FIBER_SEL 28
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#define CFG_GPIO_SFP0_PRESENT_ 30
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#define CFG_GPIO_SFP1_PRESENT_ 31
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#define CFG_GPIO_SFP0_TX_EN_ 32
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#define CFG_GPIO_SFP1_TX_EN_ 33
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#define CFG_GPIO_PHY0_EN 45
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#define CFG_GPIO_PHY1_EN 46
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#define CFG_GPIO_RESET_PRESSED_ 47
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/*
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* PPC440 GPIO Configuration
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*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
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{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
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{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
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{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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} \
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}
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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