upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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363 lines
15 KiB
363 lines
15 KiB
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* makalu.h - configuration for AMCC Makalu (405EX)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_MAKALU 1 /* Board is Makalu */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EX 1 /* Specifc 405EX support*/
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#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME makalu
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#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_BASE 0xFC000000
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#define CFG_FPGA_BASE 0xF0000000
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#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
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/*-----------------------------------------------------------------------
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* Initial RAM & Stack Pointer Configuration Options
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*
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* There are traditionally three options for the primordial
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* (i.e. initial) stack usage on the 405-series:
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*
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* 1) On-chip Memory (OCM) (i.e. SRAM)
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* 2) Data cache
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* 3) SDRAM
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*
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* For the 405EX(r), there is no OCM, so we are left with (2) or (3)
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* the latter of which is less than desireable since it requires
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* setting up the SDRAM and ECC in assembly code.
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*
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* To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
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* select on the External Bus Controller (EBC) and then select a
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* value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
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* physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
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* select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
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* physical SDRAM to use (3).
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*-----------------------------------------------------------------------*/
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#define CFG_INIT_DCACHE_CS 4
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#if defined(CFG_INIT_DCACHE_CS)
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#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
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#else
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#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
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#endif /* defined(CFG_INIT_DCACHE_CS) */
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#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*
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* If the data cache is being used for the primordial stack and global
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* data area, the POST word must be placed somewhere else. The General
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* Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
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* its compare and mask register contents across reset, so it is used
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* for the POST word.
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*/
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#if defined(CFG_INIT_DCACHE_CS)
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# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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#else
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# define CFG_INIT_EXTRA_SIZE 16
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# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
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# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
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# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
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#endif /* defined(CFG_INIT_DCACHE_CS) */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
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#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE)
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/* DDR1/2 SDRAM Device Control Register Data Values */
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#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
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SDRAM_RXBAS_SDSZ_128MB | \
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SDRAM_RXBAS_SDAM_MODE2 | \
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SDRAM_RXBAS_SDBE_ENABLE)
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#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) | \
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SDRAM_RXBAS_SDSZ_128MB | \
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SDRAM_RXBAS_SDAM_MODE2 | \
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SDRAM_RXBAS_SDBE_ENABLE)
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#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
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#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
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#define CFG_SDRAM0_MCOPT1 0x04322000
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#define CFG_SDRAM0_MCOPT2 0x00000000
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#define CFG_SDRAM0_MODT0 0x01800000
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#define CFG_SDRAM0_MODT1 0x00000000
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#define CFG_SDRAM0_CODT 0x0080f837
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#define CFG_SDRAM0_RTR 0x06180000
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#define CFG_SDRAM0_INITPLR0 0xa8380000
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#define CFG_SDRAM0_INITPLR1 0x81900400
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#define CFG_SDRAM0_INITPLR2 0x81020000
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#define CFG_SDRAM0_INITPLR3 0x81030000
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#define CFG_SDRAM0_INITPLR4 0x81010404
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#define CFG_SDRAM0_INITPLR5 0x81000542
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#define CFG_SDRAM0_INITPLR6 0x81900400
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#define CFG_SDRAM0_INITPLR7 0x8D080000
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#define CFG_SDRAM0_INITPLR8 0x8D080000
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#define CFG_SDRAM0_INITPLR9 0x8D080000
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#define CFG_SDRAM0_INITPLR10 0x8D080000
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#define CFG_SDRAM0_INITPLR11 0x81000442
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#define CFG_SDRAM0_INITPLR12 0x81010780
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#define CFG_SDRAM0_INITPLR13 0x81010400
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#define CFG_SDRAM0_INITPLR14 0x00000000
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#define CFG_SDRAM0_INITPLR15 0x00000000
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#define CFG_SDRAM0_RQDC 0x80000038
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#define CFG_SDRAM0_RFDC 0x00000209
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#define CFG_SDRAM0_RDCC 0x40000000
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#define CFG_SDRAM0_DLCR 0x030000a5
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#define CFG_SDRAM0_CLKTR 0x80000000
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#define CFG_SDRAM0_WRDTR 0x00000000
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#define CFG_SDRAM0_SDTR1 0x80201000
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#define CFG_SDRAM0_SDTR2 0x32204232
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#define CFG_SDRAM0_SDTR3 0x080b0d1a
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#define CFG_SDRAM0_MMODE 0x00000442
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#define CFG_SDRAM0_MEMODE 0x00000404
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* Standard DTT sensor configuration */
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#define CONFIG_DTT_DS1775 1
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#define CONFIG_DTT_SENSORS { 0 }
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#define CFG_I2C_DTT_ADDR 0x48
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/* RTC configuration */
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#define CONFIG_RTC_X1205 1
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#define CFG_I2C_RTC_ADDR 0x6f
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/*-----------------------------------------------------------------------
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* Ethernet
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*----------------------------------------------------------------------*/
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#define CONFIG_M88E1111_PHY 1
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
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#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 0
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_LOG
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SNTP
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ETHER | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_UART)
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/* Define here the base-addresses of the UARTs to test in POST */
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#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
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#define CONFIG_LOGBUFFER
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#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*----------------------------------------------------------------------*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/*-----------------------------------------------------------------------
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* PCIe stuff
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*----------------------------------------------------------------------*/
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#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
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#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
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#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
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#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
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#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
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#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
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#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
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#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
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#define CFG_PCIE0_UTLBASE 0xef502000
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#define CFG_PCIE1_UTLBASE 0xef503000
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/* base address of inbound PCIe window */
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#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x08033700
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#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
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/* Memory Bank 2 (CPLD) initialization */
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#define CFG_EBC_PB2AP 0x9400C800
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
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} \
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}
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#define CFG_GPIO_PCIE_RST 23
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#define CFG_GPIO_PCIE_CLKREQ 27
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#define CFG_GPIO_PCIE_WAKE 28
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#endif /* __CONFIG_H */
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