upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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379 lines
10 KiB
379 lines
10 KiB
/*
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* U-boot - traps.c Routines related to interrupts and exceptions
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* This file is based on
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* No original Copyright holder listed,
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* Probabily original (C) Roman Zippel (assigned DJD, 1999)
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*
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* Copyright 2003 Metrowerks - for Blackfin
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* Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
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* Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <linux/types.h>
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#include <asm/traps.h>
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#include <asm/cplb.h>
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#include <asm/io.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/mpu.h>
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#include <asm/mach-common/bits/trace.h>
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#include "cpu.h"
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#define trace_buffer_save(x) \
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do { \
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(x) = bfin_read_TBUFCTL(); \
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bfin_write_TBUFCTL((x) & ~TBUFEN); \
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} while (0)
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#define trace_buffer_restore(x) \
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bfin_write_TBUFCTL((x))
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/* The purpose of this map is to provide a mapping of address<->cplb settings
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* rather than an exact map of what is actually addressable on the part. This
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* map covers all current Blackfin parts. If you try to access an address that
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* is in this map but not actually on the part, you won't get an exception and
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* reboot, you'll get an external hardware addressing error and reboot. Since
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* only the ends matter (you did something wrong and the board reset), the means
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* are largely irrelevant.
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*/
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struct memory_map {
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uint32_t start, end;
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uint32_t data_flags, inst_flags;
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};
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const struct memory_map const bfin_memory_map[] = {
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{ /* external memory */
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.start = 0x00000000,
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.end = 0x20000000,
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.data_flags = SDRAM_DGENERIC,
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.inst_flags = SDRAM_IGENERIC,
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},
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{ /* async banks */
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.start = 0x20000000,
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.end = 0x30000000,
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.data_flags = SDRAM_EBIU,
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.inst_flags = SDRAM_INON_CHBL,
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},
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{ /* everything on chip */
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.start = 0xE0000000,
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.end = 0xFFFFFFFF,
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.data_flags = L1_DMEMORY,
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.inst_flags = L1_IMEMORY,
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}
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};
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void trap_c(struct pt_regs *regs)
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{
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uint32_t trapnr = (regs->seqstat & EXCAUSE);
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bool data = false;
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switch (trapnr) {
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/* 0x26 - Data CPLB Miss */
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case VEC_CPLB_M:
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if (ANOMALY_05000261) {
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static uint32_t last_cplb_fault_retx;
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/*
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* Work around an anomaly: if we see a new DCPLB fault,
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* return without doing anything. Then,
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* if we get the same fault again, handle it.
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*/
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if (last_cplb_fault_retx != regs->retx) {
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last_cplb_fault_retx = regs->retx;
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return;
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}
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}
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data = true;
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/* fall through */
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/* 0x27 - Instruction CPLB Miss */
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case VEC_CPLB_I_M: {
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volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
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uint32_t new_cplb_addr = 0, new_cplb_data = 0;
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static size_t last_evicted;
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size_t i;
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new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
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for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
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/* if the exception is inside this range, lets use it */
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if (new_cplb_addr >= bfin_memory_map[i].start &&
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new_cplb_addr < bfin_memory_map[i].end)
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break;
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}
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if (i == ARRAY_SIZE(bfin_memory_map)) {
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printf("%cCPLB exception outside of memory map at 0x%p\n",
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(data ? 'D' : 'I'), (void *)new_cplb_addr);
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bfin_panic(regs);
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} else
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debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
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new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
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if (data) {
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CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
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CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
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} else {
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CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
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CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
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}
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/* find the next unlocked entry and evict it */
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i = last_evicted & 0xF;
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debug("last evicted = %i\n", i);
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CPLB_DATA = CPLB_DATA_BASE + i;
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while (*CPLB_DATA & CPLB_LOCK) {
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debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
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i = (i + 1) & 0xF; /* wrap around */
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CPLB_DATA = CPLB_DATA_BASE + i;
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}
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CPLB_ADDR = CPLB_ADDR_BASE + i;
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debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
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last_evicted = i + 1;
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/* need to turn off cplbs whenever we muck with the cplb table */
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#if ENDCPLB != ENICPLB
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# error cplb enable bit violates my sanity
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#endif
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uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
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bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
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*CPLB_ADDR = new_cplb_addr;
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*CPLB_DATA = new_cplb_data;
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bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
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SSYNC();
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/* dump current table for debugging purposes */
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CPLB_ADDR = CPLB_ADDR_BASE;
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CPLB_DATA = CPLB_DATA_BASE;
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for (i = 0; i < 16; ++i)
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debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
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break;
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}
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default:
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/* All traps come here */
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bfin_panic(regs);
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}
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}
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#ifdef CONFIG_DEBUG_DUMP
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# define ENABLE_DUMP 1
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#else
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# define ENABLE_DUMP 0
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#endif
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#ifdef CONFIG_DEBUG_DUMP_SYMS
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# define ENABLE_DUMP_SYMS 1
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#else
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# define ENABLE_DUMP_SYMS 0
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#endif
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static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
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{
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if (!ENABLE_DUMP_SYMS)
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return NULL;
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extern const char system_map[] __attribute__((__weak__));
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const char *sym, *csym;
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char *esym;
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unsigned long sym_addr;
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sym = system_map;
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csym = NULL;
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*caddr = 0;
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while (*sym) {
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sym_addr = simple_strtoul(sym, &esym, 16);
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sym = esym;
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if (sym_addr > addr)
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break;
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*caddr = sym_addr;
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csym = sym;
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sym += strlen(sym) + 1;
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}
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return csym;
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}
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static void decode_address(char *buf, unsigned long address)
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{
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unsigned long sym_addr;
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void *paddr = (void *)address;
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const char *sym = symbol_lookup(address, &sym_addr);
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if (sym) {
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sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
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return;
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}
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if (!address)
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sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
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else if (address >= CONFIG_SYS_MONITOR_BASE &&
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address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
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else
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sprintf(buf, "<0x%p> /* unknown address */", paddr);
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}
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static char *strhwerrcause(uint16_t hwerrcause)
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{
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switch (hwerrcause) {
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case 0x02: return "system mmr error";
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case 0x03: return "external memory addressing error";
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case 0x12: return "performance monitor overflow";
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case 0x18: return "raise 5 instruction";
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default: return "undef";
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}
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}
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static char *strexcause(uint16_t excause)
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{
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switch (excause) {
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case 0x00 ... 0xf: return "custom exception";
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case 0x10: return "single step";
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case 0x11: return "trace buffer full";
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case 0x21: return "undef inst";
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case 0x22: return "illegal inst";
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case 0x23: return "dcplb prot violation";
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case 0x24: return "misaligned data";
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case 0x25: return "unrecoverable event";
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case 0x26: return "dcplb miss";
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case 0x27: return "multiple dcplb hit";
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case 0x28: return "emulation watchpoint";
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case 0x2a: return "misaligned inst";
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case 0x2b: return "icplb prot violation";
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case 0x2c: return "icplb miss";
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case 0x2d: return "multiple icplb hit";
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case 0x2e: return "illegal use of supervisor resource";
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default: return "undef";
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}
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}
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void dump(struct pt_regs *fp)
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{
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char buf[150];
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int i;
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uint16_t hwerrcause, excause;
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if (!ENABLE_DUMP)
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return;
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/* fp->ipend is garbage, so load it ourself */
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fp->ipend = bfin_read_IPEND();
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hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
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excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
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printf("SEQUENCER STATUS:\n");
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printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
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fp->seqstat, fp->ipend, fp->syscfg);
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printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
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printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
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for (i = 6; i <= 15; ++i) {
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if (fp->ipend & (1 << i)) {
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decode_address(buf, bfin_read32(EVT0 + 4*i));
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printf(" physical IVG%i asserted : %s\n", i, buf);
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}
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}
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decode_address(buf, fp->rete);
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printf(" RETE: %s\n", buf);
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decode_address(buf, fp->retn);
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printf(" RETN: %s\n", buf);
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decode_address(buf, fp->retx);
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printf(" RETX: %s\n", buf);
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decode_address(buf, fp->rets);
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printf(" RETS: %s\n", buf);
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/* we lie and store RETI in "pc" */
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decode_address(buf, fp->pc);
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printf(" RETI: %s\n", buf);
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if (fp->seqstat & EXCAUSE) {
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decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
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printf("DCPLB_FAULT_ADDR: %s\n", buf);
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decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
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printf("ICPLB_FAULT_ADDR: %s\n", buf);
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}
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printf("\nPROCESSOR STATE:\n");
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printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
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fp->r0, fp->r1, fp->r2, fp->r3);
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printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
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fp->r4, fp->r5, fp->r6, fp->r7);
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printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
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fp->p0, fp->p1, fp->p2, fp->p3);
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printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
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fp->p4, fp->p5, fp->fp, (unsigned long)fp);
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printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
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fp->lb0, fp->lt0, fp->lc0);
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printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
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fp->lb1, fp->lt1, fp->lc1);
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printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
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fp->b0, fp->l0, fp->m0, fp->i0);
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printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
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fp->b1, fp->l1, fp->m1, fp->i1);
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printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
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fp->b2, fp->l2, fp->m2, fp->i2);
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printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
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fp->b3, fp->l3, fp->m3, fp->i3);
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printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
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fp->a0w, fp->a0x, fp->a1w, fp->a1x);
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printf("USP : %08lx ASTAT: %08lx\n",
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fp->usp, fp->astat);
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printf("\n");
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}
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void dump_bfin_trace_buffer(void)
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{
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char buf[150];
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unsigned long tflags;
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int i = 0;
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if (!ENABLE_DUMP)
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return;
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trace_buffer_save(tflags);
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printf("Hardware Trace:\n");
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if (bfin_read_TBUFSTAT() & TBUFCNT) {
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for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
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decode_address(buf, bfin_read_TBUF());
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printf("%4i Target : %s\n", i, buf);
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decode_address(buf, bfin_read_TBUF());
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printf(" Source : %s\n", buf);
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}
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}
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trace_buffer_restore(tflags);
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}
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void bfin_panic(struct pt_regs *regs)
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{
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if (ENABLE_DUMP) {
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unsigned long tflags;
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trace_buffer_save(tflags);
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}
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puts(
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"\n"
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"\n"
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"\n"
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"Ack! Something bad happened to the Blackfin!\n"
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"\n"
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);
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dump(regs);
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dump_bfin_trace_buffer();
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puts("\n");
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bfin_reset_or_hang();
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}
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