upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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632 lines
15 KiB
632 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Micrel KS8851_MLL 16bit Network driver
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* Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "ks8851_mll.h"
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#define DRIVERNAME "ks8851_mll"
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#define MAX_RECV_FRAMES 32
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#define MAX_BUF_SIZE 2048
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#define TX_BUF_SIZE 2000
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#define RX_BUF_SIZE 2000
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static const struct chip_id chip_ids[] = {
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{CIDER_ID, "KSZ8851"},
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{0, NULL},
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};
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/*
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* union ks_tx_hdr - tx header data
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* @txb: The header as bytes
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* @txw: The header as 16bit, little-endian words
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*
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* A dual representation of the tx header data to allow
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* access to individual bytes, and to allow 16bit accesses
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* with 16bit alignment.
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*/
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union ks_tx_hdr {
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u8 txb[4];
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__le16 txw[2];
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};
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/*
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* struct ks_net - KS8851 driver private data
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* @net_device : The network device we're bound to
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* @txh : temporaly buffer to save status/length.
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* @frame_head_info : frame header information for multi-pkt rx.
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* @statelock : Lock on this structure for tx list.
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* @msg_enable : The message flags controlling driver output (see ethtool).
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* @frame_cnt : number of frames received.
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* @bus_width : i/o bus width.
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* @irq : irq number assigned to this device.
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* @rc_rxqcr : Cached copy of KS_RXQCR.
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* @rc_txcr : Cached copy of KS_TXCR.
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* @rc_ier : Cached copy of KS_IER.
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* @sharedbus : Multipex(addr and data bus) mode indicator.
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* @cmd_reg_cache : command register cached.
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* @cmd_reg_cache_int : command register cached. Used in the irq handler.
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* @promiscuous : promiscuous mode indicator.
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* @all_mcast : mutlicast indicator.
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* @mcast_lst_size : size of multicast list.
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* @mcast_lst : multicast list.
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* @mcast_bits : multicast enabed.
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* @mac_addr : MAC address assigned to this device.
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* @fid : frame id.
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* @extra_byte : number of extra byte prepended rx pkt.
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* @enabled : indicator this device works.
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*/
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/* Receive multiplex framer header info */
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struct type_frame_head {
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u16 sts; /* Frame status */
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u16 len; /* Byte count */
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} fr_h_i[MAX_RECV_FRAMES];
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struct ks_net {
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struct net_device *netdev;
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union ks_tx_hdr txh;
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struct type_frame_head *frame_head_info;
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u32 msg_enable;
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u32 frame_cnt;
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int bus_width;
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int irq;
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u16 rc_rxqcr;
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u16 rc_txcr;
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u16 rc_ier;
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u16 sharedbus;
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u16 cmd_reg_cache;
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u16 cmd_reg_cache_int;
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u16 promiscuous;
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u16 all_mcast;
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u16 mcast_lst_size;
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u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
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u8 mcast_bits[HW_MCAST_SIZE];
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u8 mac_addr[6];
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u8 fid;
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u8 extra_byte;
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u8 enabled;
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} ks_str, *ks;
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#define BE3 0x8000 /* Byte Enable 3 */
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#define BE2 0x4000 /* Byte Enable 2 */
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#define BE1 0x2000 /* Byte Enable 1 */
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#define BE0 0x1000 /* Byte Enable 0 */
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static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
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{
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u8 shift_bit = offset & 0x03;
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u8 shift_data = (offset & 1) << 3;
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writew(offset | (BE0 << shift_bit), dev->iobase + 2);
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return (u8)(readw(dev->iobase) >> shift_data);
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}
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static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
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return readw(dev->iobase);
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}
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static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
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{
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u8 shift_bit = (offset & 0x03);
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u16 value_write = (u16)(val << ((offset & 1) << 3));
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writew(offset | (BE0 << shift_bit), dev->iobase + 2);
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writew(value_write, dev->iobase);
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}
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static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
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writew(val, dev->iobase);
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}
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/*
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* ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
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* enabled.
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* @ks: The chip state
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* @wptr: buffer address to save data
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* @len: length in byte to read
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*/
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static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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*wptr++ = readw(dev->iobase);
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}
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/*
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* ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
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* @ks: The chip information
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* @wptr: buffer address
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* @len: length in byte to write
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*/
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static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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writew(*wptr++, dev->iobase);
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}
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static void ks_enable_int(struct eth_device *dev)
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{
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ks_wrreg16(dev, KS_IER, ks->rc_ier);
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}
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static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
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{
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unsigned pmecr;
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ks_rdreg16(dev, KS_GRR);
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pmecr = ks_rdreg16(dev, KS_PMECR);
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pmecr &= ~PMECR_PM_MASK;
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pmecr |= pwrmode;
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ks_wrreg16(dev, KS_PMECR, pmecr);
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}
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/*
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* ks_read_config - read chip configuration of bus width.
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* @ks: The chip information
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*/
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static void ks_read_config(struct eth_device *dev)
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{
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u16 reg_data = 0;
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/* Regardless of bus width, 8 bit read should always work. */
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reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
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reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
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/* addr/data bus are multiplexed */
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ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
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/*
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* There are garbage data when reading data from QMU,
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* depending on bus-width.
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*/
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if (reg_data & CCR_8BIT) {
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ks->bus_width = ENUM_BUS_8BIT;
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ks->extra_byte = 1;
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} else if (reg_data & CCR_16BIT) {
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ks->bus_width = ENUM_BUS_16BIT;
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ks->extra_byte = 2;
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} else {
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ks->bus_width = ENUM_BUS_32BIT;
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ks->extra_byte = 4;
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}
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}
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/*
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* ks_soft_reset - issue one of the soft reset to the device
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* @ks: The device state.
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* @op: The bit(s) to set in the GRR
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*
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* Issue the relevant soft-reset command to the device's GRR register
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* specified by @op.
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*
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* Note, the delays are in there as a caution to ensure that the reset
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* has time to take effect and then complete. Since the datasheet does
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* not currently specify the exact sequence, we have chosen something
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* that seems to work with our device.
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*/
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static void ks_soft_reset(struct eth_device *dev, unsigned op)
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{
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/* Disable interrupt first */
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ks_wrreg16(dev, KS_IER, 0x0000);
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ks_wrreg16(dev, KS_GRR, op);
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mdelay(10); /* wait a short time to effect reset */
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ks_wrreg16(dev, KS_GRR, 0);
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mdelay(1); /* wait for condition to clear */
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}
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void ks_enable_qmu(struct eth_device *dev)
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{
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u16 w;
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w = ks_rdreg16(dev, KS_TXCR);
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/* Enables QMU Transmit (TXCR). */
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ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
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/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
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w = ks_rdreg16(dev, KS_RXQCR);
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ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
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/* Enables QMU Receive (RXCR1). */
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w = ks_rdreg16(dev, KS_RXCR1);
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ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
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}
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static void ks_disable_qmu(struct eth_device *dev)
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{
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u16 w;
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w = ks_rdreg16(dev, KS_TXCR);
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/* Disables QMU Transmit (TXCR). */
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w &= ~TXCR_TXE;
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ks_wrreg16(dev, KS_TXCR, w);
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/* Disables QMU Receive (RXCR1). */
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w = ks_rdreg16(dev, KS_RXCR1);
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w &= ~RXCR1_RXE;
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ks_wrreg16(dev, KS_RXCR1, w);
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}
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static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
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{
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u32 r = ks->extra_byte & 0x1;
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u32 w = ks->extra_byte - r;
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/* 1. set sudo DMA mode */
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
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ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
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/*
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* 2. read prepend data
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*
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* read 4 + extra bytes and discard them.
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* extra bytes for dummy, 2 for status, 2 for len
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*/
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if (r)
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ks_rdreg8(dev, 0);
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ks_inblk(dev, buf, w + 2 + 2);
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/* 3. read pkt data */
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ks_inblk(dev, buf, ALIGN(len, 4));
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/* 4. reset sudo DMA Mode */
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ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
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}
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static void ks_rcv(struct eth_device *dev, uchar **pv_data)
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{
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struct type_frame_head *frame_hdr = ks->frame_head_info;
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int i;
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ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
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/* read all header information */
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for (i = 0; i < ks->frame_cnt; i++) {
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/* Checking Received packet status */
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frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
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/* Get packet len from hardware */
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frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
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frame_hdr++;
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}
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frame_hdr = ks->frame_head_info;
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while (ks->frame_cnt--) {
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if ((frame_hdr->sts & RXFSHR_RXFV) &&
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(frame_hdr->len < RX_BUF_SIZE) &&
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frame_hdr->len) {
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/* read data block including CRC 4 bytes */
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ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
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/* net_rx_packets buffer size is ok (*pv_data) */
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net_process_received_packet(*pv_data, frame_hdr->len);
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pv_data++;
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} else {
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ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
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printf(DRIVERNAME ": bad packet\n");
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}
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frame_hdr++;
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}
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}
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/*
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* ks_read_selftest - read the selftest memory info.
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* @ks: The device state
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*
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* Read and check the TX/RX memory selftest information.
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*/
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static int ks_read_selftest(struct eth_device *dev)
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{
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u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
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u16 mbir;
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int ret = 0;
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mbir = ks_rdreg16(dev, KS_MBIR);
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if ((mbir & both_done) != both_done) {
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printf(DRIVERNAME ": Memory selftest not finished\n");
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return 0;
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}
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if (mbir & MBIR_TXMBFA) {
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printf(DRIVERNAME ": TX memory selftest fails\n");
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ret |= 1;
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}
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if (mbir & MBIR_RXMBFA) {
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printf(DRIVERNAME ": RX memory selftest fails\n");
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ret |= 2;
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}
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debug(DRIVERNAME ": the selftest passes\n");
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return ret;
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}
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static void ks_setup(struct eth_device *dev)
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{
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u16 w;
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/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
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ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
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/* Setup Receive Frame Data Pointer Auto-Increment */
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
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/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
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ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
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/* Setup RxQ Command Control (RXQCR) */
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ks->rc_rxqcr = RXQCR_CMD_CNTL;
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ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
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/*
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* set the force mode to half duplex, default is full duplex
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* because if the auto-negotiation fails, most switch uses
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* half-duplex.
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*/
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w = ks_rdreg16(dev, KS_P1MBCR);
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w &= ~P1MBCR_FORCE_FDX;
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ks_wrreg16(dev, KS_P1MBCR, w);
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w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
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ks_wrreg16(dev, KS_TXCR, w);
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w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
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/* Normal mode */
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w |= RXCR1_RXPAFMA;
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ks_wrreg16(dev, KS_RXCR1, w);
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}
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static void ks_setup_int(struct eth_device *dev)
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{
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ks->rc_ier = 0x00;
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/* Clear the interrupts status of the hardware. */
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ks_wrreg16(dev, KS_ISR, 0xffff);
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/* Enables the interrupts of the hardware. */
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ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
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}
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static int ks8851_mll_detect_chip(struct eth_device *dev)
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{
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unsigned short val, i;
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ks_read_config(dev);
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val = ks_rdreg16(dev, KS_CIDER);
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if (val == 0xffff) {
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/* Special case -- no chip present */
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printf(DRIVERNAME ": is chip mounted ?\n");
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return -1;
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} else if ((val & 0xfff0) != CIDER_ID) {
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printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
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return -1;
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}
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debug("Read back KS8851 id 0x%x\n", val);
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/* only one entry in the table */
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val &= 0xfff0;
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for (i = 0; chip_ids[i].id != 0; i++) {
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if (chip_ids[i].id == val)
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break;
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}
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if (!chip_ids[i].id) {
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printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
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return -1;
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}
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dev->priv = (void *)&chip_ids[i];
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return 0;
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}
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static void ks8851_mll_reset(struct eth_device *dev)
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{
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/* wake up powermode to normal mode */
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ks_set_powermode(dev, PMECR_PM_NORMAL);
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mdelay(1); /* wait for normal mode to take effect */
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/* Disable interrupt and reset */
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ks_soft_reset(dev, GRR_GSR);
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/* turn off the IRQs and ack any outstanding */
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ks_wrreg16(dev, KS_IER, 0x0000);
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ks_wrreg16(dev, KS_ISR, 0xffff);
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/* shutdown RX/TX QMU */
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ks_disable_qmu(dev);
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}
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static void ks8851_mll_phy_configure(struct eth_device *dev)
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{
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u16 data;
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ks_setup(dev);
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ks_setup_int(dev);
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/* Probing the phy */
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data = ks_rdreg16(dev, KS_OBCR);
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ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
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debug(DRIVERNAME ": phy initialized\n");
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}
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static void ks8851_mll_enable(struct eth_device *dev)
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{
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ks_wrreg16(dev, KS_ISR, 0xffff);
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ks_enable_int(dev);
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ks_enable_qmu(dev);
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}
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static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
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{
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struct chip_id *id = dev->priv;
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debug(DRIVERNAME ": detected %s controller\n", id->name);
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if (ks_read_selftest(dev)) {
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printf(DRIVERNAME ": Selftest failed\n");
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return -1;
|
|
}
|
|
|
|
ks8851_mll_reset(dev);
|
|
|
|
/* Configure the PHY, initialize the link state */
|
|
ks8851_mll_phy_configure(dev);
|
|
|
|
/* static allocation of private informations */
|
|
ks->frame_head_info = fr_h_i;
|
|
|
|
/* Turn on Tx + Rx */
|
|
ks8851_mll_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
|
|
{
|
|
/* start header at txb[0] to align txw entries */
|
|
ks->txh.txw[0] = 0;
|
|
ks->txh.txw[1] = cpu_to_le16(len);
|
|
|
|
/* 1. set sudo-DMA mode */
|
|
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
|
|
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
|
|
/* 2. write status/lenth info */
|
|
ks_outblk(dev, ks->txh.txw, 4);
|
|
/* 3. write pkt data */
|
|
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
|
|
/* 4. reset sudo-DMA mode */
|
|
ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
|
|
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
|
|
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
|
|
/* 6. wait until TXQCR_METFE is auto-cleared */
|
|
do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
|
|
}
|
|
|
|
static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
u8 *data = (u8 *)packet;
|
|
u16 tmplen = (u16)length;
|
|
u16 retv;
|
|
|
|
/*
|
|
* Extra space are required:
|
|
* 4 byte for alignment, 4 for status/length, 4 for CRC
|
|
*/
|
|
retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
|
|
if (retv >= tmplen + 12) {
|
|
ks_write_qmu(dev, data, tmplen);
|
|
return 0;
|
|
} else {
|
|
printf(DRIVERNAME ": failed to send packet: No buffer\n");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
static void ks8851_mll_halt(struct eth_device *dev)
|
|
{
|
|
ks8851_mll_reset(dev);
|
|
}
|
|
|
|
/*
|
|
* Maximum receive ring size; that is, the number of packets
|
|
* we can buffer before overflow happens. Basically, this just
|
|
* needs to be enough to prevent a packet being discarded while
|
|
* we are processing the previous one.
|
|
*/
|
|
static int ks8851_mll_recv(struct eth_device *dev)
|
|
{
|
|
u16 status;
|
|
|
|
status = ks_rdreg16(dev, KS_ISR);
|
|
|
|
ks_wrreg16(dev, KS_ISR, status);
|
|
|
|
if ((status & IRQ_RXI))
|
|
ks_rcv(dev, (uchar **)net_rx_packets);
|
|
|
|
if ((status & IRQ_LDI)) {
|
|
u16 pmecr = ks_rdreg16(dev, KS_PMECR);
|
|
pmecr &= ~PMECR_WKEVT_MASK;
|
|
ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks8851_mll_write_hwaddr(struct eth_device *dev)
|
|
{
|
|
u16 addrl, addrm, addrh;
|
|
|
|
addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
|
|
addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
|
|
addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
|
|
|
|
ks_wrreg16(dev, KS_MARH, addrh);
|
|
ks_wrreg16(dev, KS_MARM, addrm);
|
|
ks_wrreg16(dev, KS_MARL, addrl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ks8851_mll_initialize(u8 dev_num, int base_addr)
|
|
{
|
|
struct eth_device *dev;
|
|
|
|
dev = malloc(sizeof(*dev));
|
|
if (!dev) {
|
|
printf("Error: Failed to allocate memory\n");
|
|
return -1;
|
|
}
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
dev->iobase = base_addr;
|
|
|
|
ks = &ks_str;
|
|
|
|
/* Try to detect chip. Will fail if not present. */
|
|
if (ks8851_mll_detect_chip(dev)) {
|
|
free(dev);
|
|
return -1;
|
|
}
|
|
|
|
dev->init = ks8851_mll_init;
|
|
dev->halt = ks8851_mll_halt;
|
|
dev->send = ks8851_mll_send;
|
|
dev->recv = ks8851_mll_recv;
|
|
dev->write_hwaddr = ks8851_mll_write_hwaddr;
|
|
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
|
|
|
|
eth_register(dev);
|
|
|
|
return 0;
|
|
}
|
|
|