upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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122 lines
4.7 KiB
122 lines
4.7 KiB
/*
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* U-boot - io.h IO routines
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*
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* Copyright (c) 2005 blackfin.uclinux.org
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _BLACKFIN_IO_H
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#define _BLACKFIN_IO_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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/* function prototypes for CF support */
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extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
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extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
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extern unsigned char cf_inb(volatile unsigned char *addr);
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extern void cf_outb(unsigned char val, volatile unsigned char* addr);
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/*
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* These are for ISA/PCI shared memory _only_ and should never be used
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* on any other type of memory, including Zorro memory. They are meant to
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* access the bus in the bus byte order which is little-endian!.
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*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the m68k architecture, we just read/write the
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* memory location directly.
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*/
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#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
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#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
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#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
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#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");}
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#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");}
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#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");}
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE)
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#define inb(addr) cf_inb((volatile unsigned char*)(addr))
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#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
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#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE)
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#define inw(addr) readw((addr) + BF533_PCIIO_BASE)
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#define inl(addr) readl((addr) + BF533_PCIIO_BASE)
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#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE)
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#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE)
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#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count)
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#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
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#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count))
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#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count)
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#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
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#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count))
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#define IO_SPACE_LIMIT 0xffff
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/* Values for nocacheflag and cmode */
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#define IOMAP_FULL_CACHING 0
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#define IOMAP_NOCACHE_SER 1
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#define IOMAP_NOCACHE_NONSER 2
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#define IOMAP_WRITETHROUGH 3
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extern void *__ioremap(unsigned long physaddr, unsigned long size,
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int cacheflag);
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extern void __iounmap(void *addr, unsigned long size);
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extern inline void *ioremap(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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extern inline void *ioremap_nocache(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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extern inline void *ioremap_writethrough(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
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}
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extern inline void *ioremap_fullcache(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
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}
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extern void iounmap(void *addr);
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extern void blkfin_inv_cache_all(void);
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#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
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#define dma_cache_wback(_start,_size) do { } while (0)
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#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
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#endif
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#endif
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