upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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117 lines
3.3 KiB
117 lines
3.3 KiB
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include "hsdramc1.h"
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unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
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{
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unsigned long sdram_size;
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uint32_t cfgreg;
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unsigned int i;
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cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
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| HSDRAMC1_BF(NR, config->row_bits - 11)
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| HSDRAMC1_BF(NB, config->bank_bits - 1)
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| HSDRAMC1_BF(CAS, config->cas)
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| HSDRAMC1_BF(TWR, config->twr)
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| HSDRAMC1_BF(TRC, config->trc)
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| HSDRAMC1_BF(TRP, config->trp)
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| HSDRAMC1_BF(TRCD, config->trcd)
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| HSDRAMC1_BF(TRAS, config->tras)
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| HSDRAMC1_BF(TXSR, config->txsr));
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if (config->data_bits == SDRAM_DATA_16BIT)
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cfgreg |= HSDRAMC1_BIT(DBW);
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hsdramc1_writel(CR, cfgreg);
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/* Send a NOP to turn on the clock (necessary on some chips) */
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hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
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hsdramc1_readl(MR);
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writel(0, sdram_base);
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/*
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* Initialization sequence for SDRAM, from the data sheet:
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*
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* 1. A minimum pause of 200 us is provided to precede any
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* signal toggle.
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*/
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udelay(200);
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/*
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* 2. A Precharge All command is issued to the SDRAM
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
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hsdramc1_readl(MR);
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writel(0, sdram_base);
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/*
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* 3. Eight auto-refresh (CBR) cycles are provided
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
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hsdramc1_readl(MR);
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for (i = 0; i < 8; i++)
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writel(0, sdram_base);
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/*
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* 4. A mode register set (MRS) cycle is issued to program
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* SDRAM parameters, in particular CAS latency and burst
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* length.
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*
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* The address will be chosen by the SDRAMC automatically; we
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* just have to make sure BA[1:0] are set to 0.
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
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hsdramc1_readl(MR);
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writel(0, sdram_base);
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/*
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* 5. The application must go into Normal Mode, setting Mode
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* to 0 in the Mode Register and performing a write access
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* at any location in the SDRAM.
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
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hsdramc1_readl(MR);
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writel(0, sdram_base);
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/*
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* 6. Write refresh rate into SDRAMC refresh timer count
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* register (refresh rate = timing between refresh cycles).
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*/
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hsdramc1_writel(TR, config->refresh_period);
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if (config->data_bits == SDRAM_DATA_16BIT)
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sdram_size = 1 << (config->row_bits + config->col_bits
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+ config->bank_bits + 1);
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else
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sdram_size = 1 << (config->row_bits + config->col_bits
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+ config->bank_bits + 2);
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return sdram_size;
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}
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