upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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92 lines
2.5 KiB
92 lines
2.5 KiB
/*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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* Copyright (C) 2007-2009 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Derived from the MPC83xx code.
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Set up the memory map, initialize registers,
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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u32 ips_div;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* system performance tweaking */
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#ifdef CONFIG_SYS_ACR_PIPE_DEP
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/* Arbiter pipeline depth */
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out_be32(&im->arbiter.acr,
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(im->arbiter.acr & ~ACR_PIPE_DEP) |
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(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
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);
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#endif
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#ifdef CONFIG_SYS_ACR_RPTCNT
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/* Arbiter repeat count */
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out_be32(im->arbiter.acr,
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(im->arbiter.acr & ~(ACR_RPTCNT)) |
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(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
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);
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#endif
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/* RSR - Reset Status Register - clear all status */
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gd->reset_status = im->reset.rsr;
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out_be32(&im->reset.rsr, ~RSR_RES);
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/*
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* RMR - Reset Mode Register - enable checkstop reset
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*/
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out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
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/* Set IPS-CSB divider: IPS = 1/2 CSB */
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ips_div = in_be32(&im->clk.scfr[0]);
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ips_div &= ~(SCFR1_IPS_DIV_MASK);
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ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
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out_be32(&im->clk.scfr[0], ips_div);
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/*
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* Enable Time Base/Decrementer
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*
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* NOTICE: TB needs to be enabled as early as possible in order to
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* have udelay() working; if not enabled, usually leads to a hang, like
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* during FLASH chip identification etc.
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*/
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setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
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}
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int cpu_init_r (void)
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{
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return 0;
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}
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