upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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343 lines
7.2 KiB
343 lines
7.2 KiB
/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fpga.h>
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#include <video_fb.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/dss.h>
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#include <asm/arch/clock.h>
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#include <i2c.h>
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#include <spartan3.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "mt_ventoux.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define BUZZER 140
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#define SPEAKER 141
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#define USB1_PWR 127
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#define USB2_PWR 149
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#ifndef CONFIG_FPGA
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#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
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#endif
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#define FPGA_RESET 62
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#define FPGA_PROG 116
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#define FPGA_CCLK 117
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#define FPGA_DIN 118
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#define FPGA_INIT 119
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#define FPGA_DONE 154
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#define LCD_PWR 138
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#define LCD_PON_PIN 139
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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static struct {
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u32 xres;
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u32 yres;
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} panel_resolution[] = {
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{ 480, 272 },
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{ 800, 480 }
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};
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static struct panel_config lcd_cfg[] = {
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{
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.timing_h = PANEL_TIMING_H(40, 5, 2),
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.timing_v = PANEL_TIMING_V(8, 8, 2),
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.pol_freq = 0x00003000, /* Pol Freq */
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.divisor = 0x00010033, /* 9 Mhz Pixel Clock */
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0,
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.gfx_format = GFXFORMAT_RGB24_UNPACKED,
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},
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{
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.timing_h = PANEL_TIMING_H(20, 192, 4),
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.timing_v = PANEL_TIMING_V(2, 20, 10),
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.pol_freq = 0x00004000, /* Pol Freq */
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.divisor = 0x0001000E, /* 36Mhz Pixel Clock */
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0,
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.gfx_format = GFXFORMAT_RGB24_UNPACKED,
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}
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};
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#endif
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/* Timing definitions for FPGA */
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static const u32 gpmc_fpga[] = {
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FPGA_GPMC_CONFIG1,
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FPGA_GPMC_CONFIG2,
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FPGA_GPMC_CONFIG3,
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FPGA_GPMC_CONFIG4,
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FPGA_GPMC_CONFIG5,
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FPGA_GPMC_CONFIG6,
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};
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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static inline void fpga_reset(int nassert)
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{
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gpio_set_value(FPGA_RESET, !nassert);
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}
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int fpga_pgm_fn(int nassert, int nflush, int cookie)
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{
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debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
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gpio_set_value(FPGA_PROG, !nassert);
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return nassert;
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}
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int fpga_init_fn(int cookie)
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{
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return !gpio_get_value(FPGA_INIT);
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}
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int fpga_done_fn(int cookie)
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{
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return gpio_get_value(FPGA_DONE);
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}
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int fpga_pre_config_fn(int cookie)
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{
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debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
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/* Setting GPIOs for programming Mode */
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gpio_request(FPGA_RESET, "FPGA_RESET");
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gpio_direction_output(FPGA_RESET, 1);
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gpio_request(FPGA_PROG, "FPGA_PROG");
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gpio_direction_output(FPGA_PROG, 1);
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gpio_request(FPGA_CCLK, "FPGA_CCLK");
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gpio_direction_output(FPGA_CCLK, 1);
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gpio_request(FPGA_DIN, "FPGA_DIN");
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gpio_direction_output(FPGA_DIN, 0);
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gpio_request(FPGA_INIT, "FPGA_INIT");
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gpio_direction_input(FPGA_INIT);
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gpio_request(FPGA_DONE, "FPGA_DONE");
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gpio_direction_input(FPGA_DONE);
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/* Be sure that signal are deasserted */
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gpio_set_value(FPGA_RESET, 1);
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gpio_set_value(FPGA_PROG, 1);
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return 0;
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}
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int fpga_post_config_fn(int cookie)
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{
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debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
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fpga_reset(true);
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udelay(100);
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fpga_reset(false);
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return 0;
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}
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/* Write program to the FPGA */
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int fpga_wr_fn(int nassert_write, int flush, int cookie)
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{
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gpio_set_value(FPGA_DIN, nassert_write);
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return nassert_write;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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gpio_set_value(FPGA_CCLK, assert_clk);
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return assert_clk;
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}
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xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_clk_fn,
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fpga_init_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_post_config_fn,
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};
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xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
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(void *)&mt_ventoux_fpga_fns, 0);
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/* Initialize the FPGA */
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static void mt_ventoux_init_fpga(void)
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{
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fpga_pre_config_fn(0);
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/* Setting CS1 for FPGA access */
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enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
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FPGA_BASE_ADDR, GPMC_SIZE_128M);
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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mt_ventoux_init_fpga();
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/* GPIO_140: speaker #mute */
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MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
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/* GPIO_141: Buzz Hi */
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MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
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/* Turning off the buzzer */
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gpio_request(BUZZER, "BUZZER_MUTE");
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gpio_request(SPEAKER, "SPEAKER");
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gpio_direction_output(BUZZER, 0);
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gpio_direction_output(SPEAKER, 0);
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/* Activate USB power */
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gpio_request(USB1_PWR, "USB1_PWR");
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gpio_request(USB2_PWR, "USB2_PWR");
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gpio_direction_output(USB1_PWR, 1);
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gpio_direction_output(USB2_PWR, 1);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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int misc_init_r(void)
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{
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char *eth_addr;
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struct tam3517_module_info info;
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int ret;
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TAM3517_READ_EEPROM(&info, ret);
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omap_die_id_display();
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if (ret)
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return 0;
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eth_addr = getenv("ethaddr");
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if (!eth_addr)
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TAM3517_READ_MAC_FROM_EEPROM(&info);
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TAM3517_PRINT_SOM_INFO(&info);
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return 0;
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}
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#endif
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_MT_VENTOUX();
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int board_eth_init(bd_t *bis)
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{
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davinci_emac_initialize();
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return 0;
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}
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#if defined(CONFIG_OMAP_HSMMC) && \
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!defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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int board_video_init(void)
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{
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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struct panel_config *panel = &lcd_cfg[0];
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char *s;
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u32 index = 0;
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void *fb;
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fb = (void *)0x88000000;
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s = getenv("panel");
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if (s) {
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index = simple_strtoul(s, NULL, 10);
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if (index < ARRAY_SIZE(lcd_cfg))
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panel = &lcd_cfg[index];
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else
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return 0;
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}
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panel->frame_buffer = fb;
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printf("Panel: %dx%d\n", panel_resolution[index].xres,
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panel_resolution[index].yres);
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panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
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(panel_resolution[index].xres - 1);
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gpio_request(LCD_PWR, "LCD Power");
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gpio_request(LCD_PON_PIN, "LCD Pon");
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gpio_direction_output(LCD_PWR, 0);
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gpio_direction_output(LCD_PON_PIN, 1);
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setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
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setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
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omap3_dss_panel_config(panel);
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omap3_dss_enable();
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return 0;
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}
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#endif
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