upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.5 KiB
149 lines
3.5 KiB
/*
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* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some board init for the Allwinner A10-evb board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#ifdef CONFIG_AXP209_POWER
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#include <axp209.h>
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#endif
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* add board specific code here */
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int board_init(void)
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{
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int id_pfr1;
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gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
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asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
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debug("id_pfr1: 0x%08x\n", id_pfr1);
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/* Generic Timer Extension available? */
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if ((id_pfr1 >> 16) & 0xf) {
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debug("Setting CNTFRQ\n");
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/* CNTFRQ == 24 MHz */
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
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}
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
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return 0;
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}
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#ifdef CONFIG_GENERIC_MMC
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static void mmc_pinmux_setup(int sdc)
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{
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unsigned int pin;
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switch (sdc) {
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case 0:
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/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
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for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 1:
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/* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
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for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 2:
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/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 3:
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/* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
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for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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default:
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printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
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break;
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}
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}
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int board_mmc_init(bd_t *bis)
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{
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
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sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
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#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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#endif
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return 0;
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}
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#endif
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void i2c_init_board(void)
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{
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
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clock_twi_onoff(0, 1);
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}
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#ifdef CONFIG_SPL_BUILD
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void sunxi_board_init(void)
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{
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int power_failed = 0;
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unsigned long ramsize;
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#ifdef CONFIG_AXP209_POWER
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power_failed |= axp209_init();
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power_failed |= axp209_set_dcdc2(1400);
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power_failed |= axp209_set_dcdc3(1250);
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power_failed |= axp209_set_ldo2(3000);
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power_failed |= axp209_set_ldo3(2800);
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power_failed |= axp209_set_ldo4(2800);
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#endif
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printf("DRAM:");
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ramsize = sunxi_dram_init();
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printf(" %lu MiB\n", ramsize >> 20);
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if (!ramsize)
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hang();
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/*
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* Only clock up the CPU to full speed if we are reasonably
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* assured it's being powered with suitable core voltage
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*/
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if (!power_failed)
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clock_set_pll1(CONFIG_CLK_FULL_SPEED);
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else
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printf("Failed to set core voltage! Can't set CPU frequency\n");
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}
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#endif
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