upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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634 lines
17 KiB
634 lines
17 KiB
/*
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* NAND driver for TI DaVinci based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
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*/
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/*
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*
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* linux/drivers/mtd/nand/nand_davinci.c
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*
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* NAND Flash Driver
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* DaVinci board which utilizes the Samsung k9k2g08 part.
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*
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Modifications:
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ver. 1.0: Feb 2005, Vinod/Sudhakar
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-
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/emif_defs.h>
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/* Definitions for 4-bit hardware ECC */
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#define NAND_TIMEOUT 10240
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#define NAND_ECC_BUSY 0xC
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#define NAND_4BITECC_MASK 0x03FF03FF
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#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
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#define ECC_STATE_NO_ERR 0x0
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#define ECC_STATE_TOO_MANY_ERRS 0x1
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#define ECC_STATE_ERR_CORR_COMP_P 0x2
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#define ECC_STATE_ERR_CORR_COMP_N 0x3
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/*
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* Exploit the little endianness of the ARM to do multi-byte transfers
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* per device read. This can perform over twice as quickly as individual
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* byte transfers when buffer alignment is conducive.
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*
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* NOTE: This only works if the NAND is not connected to the 2 LSBs of
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* the address bus. On Davinci EVM platforms this has always been true.
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*/
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static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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const u32 *nand = chip->IO_ADDR_R;
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/* Make sure that buf is 32 bit aligned */
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if (((int)buf & 0x3) != 0) {
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if (((int)buf & 0x1) != 0) {
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if (len) {
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*buf = readb(nand);
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buf += 1;
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len--;
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}
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}
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if (((int)buf & 0x3) != 0) {
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if (len >= 2) {
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*(u16 *)buf = readw(nand);
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buf += 2;
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len -= 2;
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}
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}
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}
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/* copy aligned data */
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while (len >= 4) {
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*(u32 *)buf = __raw_readl(nand);
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buf += 4;
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len -= 4;
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}
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/* mop up any remaining bytes */
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if (len) {
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if (len >= 2) {
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*(u16 *)buf = readw(nand);
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buf += 2;
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len -= 2;
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}
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if (len)
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*buf = readb(nand);
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}
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}
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static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd->priv;
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const u32 *nand = chip->IO_ADDR_W;
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/* Make sure that buf is 32 bit aligned */
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if (((int)buf & 0x3) != 0) {
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if (((int)buf & 0x1) != 0) {
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if (len) {
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writeb(*buf, nand);
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buf += 1;
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len--;
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}
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}
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if (((int)buf & 0x3) != 0) {
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if (len >= 2) {
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writew(*(u16 *)buf, nand);
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buf += 2;
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len -= 2;
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}
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}
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}
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/* copy aligned data */
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while (len >= 4) {
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__raw_writel(*(u32 *)buf, nand);
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buf += 4;
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len -= 4;
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}
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/* mop up any remaining bytes */
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if (len) {
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if (len >= 2) {
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writew(*(u16 *)buf, nand);
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buf += 2;
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len -= 2;
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}
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if (len)
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writeb(*buf, nand);
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}
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}
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= MASK_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= MASK_ALE;
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this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, IO_ADDR_W);
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}
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#ifdef CONFIG_SYS_NAND_HW_ECC
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u_int32_t val;
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(void)__raw_readl(&(davinci_emif_regs->nandfecc[
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CONFIG_SYS_NAND_CS - 2]));
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val = __raw_readl(&davinci_emif_regs->nandfcr);
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val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
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__raw_writel(val, &davinci_emif_regs->nandfcr);
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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{
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u_int32_t ecc = 0;
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ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
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return ecc;
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}
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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u_int32_t tmp;
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const int region = 1;
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tmp = nand_davinci_readecc(mtd, region);
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/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
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* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
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tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
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/* Invert so that erased block ECC is correct */
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tmp = ~tmp;
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 8;
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*ecc_code++ = tmp >> 16;
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/* NOTE: the above code matches mainline Linux:
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* .PQR.stu ==> ~PQRstu
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*
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* MontaVista/TI kernels encode those bytes differently, use
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* complicated (and allegedly sometimes-wrong) correction code,
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* and usually shipped with U-Boot that uses software ECC:
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* .PQR.stu ==> PsQRtu
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*
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* If you need MV/TI compatible NAND I/O in U-Boot, it should
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* be possible to (a) change the mangling above, (b) reverse
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* that mangling in nand_davinci_correct_data() below.
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*/
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return 0;
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}
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static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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u_int32_t diff = ecc_calc ^ ecc_nand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < this->ecc.size) {
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uint8_t find_bit = 1 << ((diff >> 12) & 7);
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uint32_t find_byte = diff >> (12 + 3);
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dat[find_byte] ^= find_bit;
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
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"bit ECC error at offset: %d, bit: "
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"%d\n", find_byte, find_bit);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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nothing to fix */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
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"ECC.\n");
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return 1;
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} else {
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/* Uncorrectable error */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
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return -1;
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}
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}
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return 0;
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}
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
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#if defined(CONFIG_SYS_NAND_PAGE_2K)
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.eccbytes = 40,
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.eccpos = {
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24, 25, 26, 27, 28,
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
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59, 60, 61, 62, 63,
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},
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.oobfree = {
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{.offset = 2, .length = 22, },
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},
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#elif defined(CONFIG_SYS_NAND_PAGE_4K)
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.eccbytes = 80,
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.eccpos = {
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
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58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
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68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
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78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
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88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
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98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
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108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
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118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
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},
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.oobfree = {
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{.offset = 2, .length = 46, },
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},
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#endif
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};
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static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u32 val;
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switch (mode) {
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case NAND_ECC_WRITE:
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case NAND_ECC_READ:
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/*
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* Start a new ECC calculation for reading or writing 512 bytes
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* of data.
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*/
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val = __raw_readl(&davinci_emif_regs->nandfcr);
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val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
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val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_4BIT_ECC_START;
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__raw_writel(val, &davinci_emif_regs->nandfcr);
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break;
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case NAND_ECC_READSYN:
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val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
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break;
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default:
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break;
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}
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}
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static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
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{
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int i;
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for (i = 0; i < 4; i++) {
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ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
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NAND_4BITECC_MASK;
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}
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return 0;
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}
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static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code)
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{
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unsigned int hw_4ecc[4];
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unsigned int i;
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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/*Convert 10 bit ecc value to 8 bit */
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for (i = 0; i < 2; i++) {
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unsigned int hw_ecc_low = hw_4ecc[i * 2];
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unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
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/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
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*ecc_code++ = hw_ecc_low & 0xFF;
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/*
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* Take 2 bits as LSB bits from val1 (count1=0) or val5
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* (count1=1) and 6 bits from val2 (count1=0) or
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* val5 (count1=1)
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*/
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*ecc_code++ =
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((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
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/*
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* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
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* 4 bits from val3 (count1=0) or val6 (count1=1)
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*/
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*ecc_code++ =
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((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
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/*
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* Take 6 bits from val3(count1=0) or val6 (count1=1) and
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* 2 bits from val4 (count1=0) or val7 (count1=1)
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*/
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*ecc_code++ =
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((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
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/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
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*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
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}
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return 0;
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}
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static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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int i;
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unsigned int hw_4ecc[4];
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unsigned int iserror;
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unsigned short *ecc16;
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unsigned int numerrors, erroraddress, errorvalue;
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u32 val;
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/*
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* Check for an ECC where all bytes are 0xFF. If this is the case, we
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* will assume we are looking at an erased page and we should ignore
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* the ECC.
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*/
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for (i = 0; i < 10; i++) {
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if (read_ecc[i] != 0xFF)
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break;
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}
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if (i == 10)
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return 0;
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/* Convert 8 bit in to 10 bit */
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ecc16 = (unsigned short *)&read_ecc[0];
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/*
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* Write the parity values in the NAND Flash 4-bit ECC Load register.
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* Write each parity value one at a time starting from 4bit_ecc_val8
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* to 4bit_ecc_val1.
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*/
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/*Take 2 bits from 8th byte and 8 bits from 9th byte */
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__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
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&davinci_emif_regs->nand4biteccload);
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/* Take 4 bits from 7th byte and 6 bits from 8th byte */
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__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
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&davinci_emif_regs->nand4biteccload);
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/* Take 6 bits from 6th byte and 4 bits from 7th byte */
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__raw_writel((ecc16[3] >> 2) & 0x3FF,
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&davinci_emif_regs->nand4biteccload);
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/* Take 8 bits from 5th byte and 2 bits from 6th byte */
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__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
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&davinci_emif_regs->nand4biteccload);
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/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
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__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
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&davinci_emif_regs->nand4biteccload);
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/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
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__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
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&davinci_emif_regs->nand4biteccload);
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/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
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__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
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&davinci_emif_regs->nand4biteccload);
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/* Take 10 bits from 0th and 1st bytes */
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__raw_writel((ecc16[0]) & 0x3FF,
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&davinci_emif_regs->nand4biteccload);
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/*
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* Perform a dummy read to the EMIF Revision Code and Status register.
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* This is required to ensure time for syndrome calculation after
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* writing the ECC values in previous step.
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*/
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val = __raw_readl(&davinci_emif_regs->nandfsr);
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/*
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* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
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* A syndrome value of 0 means no bit errors. If the syndrome is
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* non-zero then go further otherwise return.
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*/
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
|
|
return 0;
|
|
|
|
/*
|
|
* Clear any previous address calculation by doing a dummy read of an
|
|
* error address register.
|
|
*/
|
|
val = __raw_readl(&davinci_emif_regs->nanderradd1);
|
|
|
|
/*
|
|
* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
|
|
* register to 1.
|
|
*/
|
|
__raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
|
|
|
|
/*
|
|
* Wait for the corr_state field (bits 8 to 11)in the
|
|
* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
|
|
*/
|
|
i = NAND_TIMEOUT;
|
|
do {
|
|
val = __raw_readl(&davinci_emif_regs->nandfsr);
|
|
val &= 0xc00;
|
|
i--;
|
|
} while ((i > 0) && val);
|
|
|
|
iserror = __raw_readl(&davinci_emif_regs->nandfsr);
|
|
iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
|
|
iserror = iserror >> 8;
|
|
|
|
/*
|
|
* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
|
|
* corrected (five or more errors). The number of errors
|
|
* calculated (err_num field) differs from the number of errors
|
|
* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
|
|
* correction complete (errors on bit 8 or 9).
|
|
* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
|
|
* complete (error exists).
|
|
*/
|
|
|
|
if (iserror == ECC_STATE_NO_ERR) {
|
|
val = __raw_readl(&davinci_emif_regs->nanderrval1);
|
|
return 0;
|
|
} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
|
|
val = __raw_readl(&davinci_emif_regs->nanderrval1);
|
|
return -1;
|
|
}
|
|
|
|
numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
|
|
& 0x3) + 1;
|
|
|
|
/* Read the error address, error value and correct */
|
|
for (i = 0; i < numerrors; i++) {
|
|
if (i > 1) {
|
|
erroraddress =
|
|
((__raw_readl(&davinci_emif_regs->nanderradd2) >>
|
|
(16 * (i & 1))) & 0x3FF);
|
|
erroraddress = ((512 + 7) - erroraddress);
|
|
errorvalue =
|
|
((__raw_readl(&davinci_emif_regs->nanderrval2) >>
|
|
(16 * (i & 1))) & 0xFF);
|
|
} else {
|
|
erroraddress =
|
|
((__raw_readl(&davinci_emif_regs->nanderradd1) >>
|
|
(16 * (i & 1))) & 0x3FF);
|
|
erroraddress = ((512 + 7) - erroraddress);
|
|
errorvalue =
|
|
((__raw_readl(&davinci_emif_regs->nanderrval1) >>
|
|
(16 * (i & 1))) & 0xFF);
|
|
}
|
|
/* xor the corrupt data with error value */
|
|
if (erroraddress < 512)
|
|
dat[erroraddress] ^= errorvalue;
|
|
}
|
|
|
|
return numerrors;
|
|
}
|
|
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
|
|
|
|
static int nand_davinci_dev_ready(struct mtd_info *mtd)
|
|
{
|
|
return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
|
|
}
|
|
|
|
static void nand_flash_init(void)
|
|
{
|
|
/* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
|
|
* Instead, have your board_init() set EMIF timings, based on its
|
|
* knowledge of the clocks and what devices are hooked up ... and
|
|
* don't even do that unless no UBL handled it.
|
|
*/
|
|
#ifdef CONFIG_SOC_DM644X
|
|
u_int32_t acfg1 = 0x3ffffffc;
|
|
|
|
/*------------------------------------------------------------------*
|
|
* NAND FLASH CHIP TIMEOUT @ 459 MHz *
|
|
* *
|
|
* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
|
|
* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
|
|
* *
|
|
*------------------------------------------------------------------*/
|
|
acfg1 = 0
|
|
| (0 << 31) /* selectStrobe */
|
|
| (0 << 30) /* extWait */
|
|
| (1 << 26) /* writeSetup 10 ns */
|
|
| (3 << 20) /* writeStrobe 40 ns */
|
|
| (1 << 17) /* writeHold 10 ns */
|
|
| (1 << 13) /* readSetup 10 ns */
|
|
| (5 << 7) /* readStrobe 60 ns */
|
|
| (1 << 4) /* readHold 10 ns */
|
|
| (3 << 2) /* turnAround ?? ns */
|
|
| (0 << 0) /* asyncSize 8-bit bus */
|
|
;
|
|
|
|
__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
|
|
|
|
/* NAND flash on CS2 */
|
|
__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
|
|
#endif
|
|
}
|
|
|
|
void davinci_nand_init(struct nand_chip *nand)
|
|
{
|
|
nand->chip_delay = 0;
|
|
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
|
|
nand->options |= NAND_USE_FLASH_BBT;
|
|
#endif
|
|
#ifdef CONFIG_SYS_NAND_HW_ECC
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.calculate = nand_davinci_calculate_ecc;
|
|
nand->ecc.correct = nand_davinci_correct_data;
|
|
nand->ecc.hwctl = nand_davinci_enable_hwecc;
|
|
#else
|
|
nand->ecc.mode = NAND_ECC_SOFT;
|
|
#endif /* CONFIG_SYS_NAND_HW_ECC */
|
|
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
|
|
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.bytes = 10;
|
|
nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
|
|
nand->ecc.correct = nand_davinci_4bit_correct_data;
|
|
nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
|
|
nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
|
|
#endif
|
|
/* Set address of hardware control function */
|
|
nand->cmd_ctrl = nand_davinci_hwcontrol;
|
|
|
|
nand->read_buf = nand_davinci_read_buf;
|
|
nand->write_buf = nand_davinci_write_buf;
|
|
|
|
nand->dev_ready = nand_davinci_dev_ready;
|
|
|
|
nand_flash_init();
|
|
}
|
|
|
|
int board_nand_init(struct nand_chip *chip) __attribute__((weak));
|
|
|
|
int board_nand_init(struct nand_chip *chip)
|
|
{
|
|
davinci_nand_init(chip);
|
|
return 0;
|
|
}
|
|
|