upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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273 lines
7.1 KiB
273 lines
7.1 KiB
/*
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* (C) Copyright 2010
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* Matthias Weisser <weisserm@arcor.de>
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*
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* Configuation settings for the jadecpu board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MB86R0x
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#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
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#define CONFIG_SYS_TEXT_BASE 0x10000000
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_USE_ARCH_MEMSET
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#define MACH_TYPE_JADECPU 2636
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#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
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/*
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* Environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"gs_fast_boot=setenv bootdelay 5\0" \
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"gs_slow_boot=setenv bootdelay 10\0" \
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"bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
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"fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
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"bootelf 0x40000000\0" \
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""
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_BOARD_LATE_INIT
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/*
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* Compressions
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*/
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#define CONFIG_LZO
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/*
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* Hardware drivers
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*/
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/*
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* Serial
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
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#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
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#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
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#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
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#define CONFIG_CONS_INDEX 4
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/*
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* Ethernet
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*/
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_BASE 0x02000000
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#define CONFIG_SMC911X_16_BIT
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/*
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* Video
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*/
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB86R0xGDC
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#define CONFIG_SYS_WHITE_ON_BLACK
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define VIDEO_KBD_INIT_FCT 0
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#define VIDEO_TSTC_FCT serial_stub_tstc
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#define VIDEO_GETC_FCT serial_stub_getc
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_XIMG
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_CACHE
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#define CONFIG_SYS_HUSH_PARSER
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/* USB */
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#define CONFIG_USB_STORAGE
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#define CONFIG_DOS_PARTITION
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_SP_ADDR 0x01008000
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE 0x10000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (128 * 1024)
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/*
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
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#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_PROMPT "jade> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_PREBOOT ""
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
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#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 << 20)
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#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
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/*
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* Clock reset generator init
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*/
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#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
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#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
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#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
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#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
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#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
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/*
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* Memory controller settings
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*/
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#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
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#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
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#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
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#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
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#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
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#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
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#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
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#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
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#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
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/*
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* DDR2 controller init settings
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*/
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#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
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#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
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#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
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#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
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#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
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#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
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#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
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#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
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#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
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#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
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#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
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#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
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#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
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#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
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#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
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#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
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/*
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* DRAM init sequence
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*/
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/* PALL Command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
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#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
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/* EMR(2) command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
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#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
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/* EMR(3) command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
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#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
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/* EMR(1) command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
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#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
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/* MRS command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
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#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
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/* PALL command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
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#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
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/* REF command 1 */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
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#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
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/* MRS command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
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#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
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/* EMR(1) command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
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#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
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/* EMR(1) command */
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#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
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#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
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#endif /* __CONFIG_H */
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