upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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507 lines
17 KiB
507 lines
17 KiB
#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0x80F00000
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/*****************************************************************************
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*
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* These settings must match the way _your_ board is set up
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*
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*****************************************************************************/
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/* for the AY-Revision which does not use the HRCW */
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#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
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/* What is the oscillator's (UX2) frequency in Hz? */
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#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
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/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
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* only the 3 least significant bits are important.
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*/
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#define CONFIG_SYS_SBC_S2 0x04
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/* What should MODCK_H be? It is dependent on the oscillator
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* frequency, MODCK[1-3], and desired CPM and core frequencies.
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* Some example values (all frequencies are in MHz):
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*
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* MODCK_H MODCK[1-3] Osc CPM Core
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* 0x2 0x2 33 133 133
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* 0x2 0x4 33 133 200
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* 0x5 0x5 66 133 133
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* 0x5 0x7 66 133 200
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*/
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#define CONFIG_SYS_SBC_MODCK_H 0x06
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#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */
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#undef CONFIG_SYS_SBC_BOOT_LOW
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/* What should the base address of the main FLASH be and how big is
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* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
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* The main FLASH is whichever is connected to *CS0. U-Boot expects
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* this to be the SIMM.
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*/
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#define CONFIG_SYS_FLASH0_BASE 0x80000000
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#define CONFIG_SYS_FLASH0_SIZE 16
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/* What should the base address of the secondary FLASH be and how big
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* is it (in Mbytes)? The secondary FLASH is whichever is connected
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* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
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* want it enabled, don't define these constants.
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*/
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#define CONFIG_SYS_FLASH1_BASE 0
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#define CONFIG_SYS_FLASH1_SIZE 0
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#undef CONFIG_SYS_FLASH1_BASE
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#undef CONFIG_SYS_FLASH1_SIZE
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)?
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*/
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#define CONFIG_SYS_SDRAM0_BASE 0x00000000
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#define CONFIG_SYS_SDRAM0_SIZE 64
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)?
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*/
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#define CONFIG_SYS_SDRAM1_BASE 0x04000000
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#define CONFIG_SYS_SDRAM1_SIZE 32
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/* What should be the base address of the LEDs and switch S0?
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* If you don't want them enabled, don't define this.
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*/
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#define CONFIG_SYS_LED_BASE 0x00000000
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere.
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*/
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on neither */
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#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
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#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
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#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
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#if ( CONFIG_ETHER_INDEX == 3 )
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/*
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* - Rx-CLK is CLK15
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* - Tx-CLK is CLK16
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Half Duplex in FSMR
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*/
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# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
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# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
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# define CONFIG_SYS_CPMFCR_RAMTYPE 0
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/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
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# define CONFIG_SYS_FCC_PSMR 0
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#else /* CONFIG_ETHER_INDEX */
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# error "on RPX Super ethernet must be FCC3"
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#endif /* CONFIG_ETHER_INDEX */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/* Define this to reserve an entire FLASH sector (256 KB) for
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* environment variables. Otherwise, the environment will be
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* put in the same sector as U-Boot, and changing variables
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* will erase U-Boot temporarily
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*/
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#define CONFIG_ENV_IN_OWN_SECT
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* What should the console's baud rate be? */
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#define CONFIG_BAUDRATE 115200
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/* Ethernet MAC address */
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#define CONFIG_ETHADDR 08:00:22:50:70:63
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#define CONFIG_IPADDR 192.168.1.99
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#define CONFIG_SERVERIP 192.168.1.3
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/* Set to a positive value to delay for running BOOTCOMMAND */
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#define CONFIG_BOOTDELAY -1
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/* undef this to save memory */
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#define CONFIG_SYS_LONGHELP
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT "=> "
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_REGINFO
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#undef CONFIG_CMD_KGDB
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/* Where do the internal registers live? */
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#define CONFIG_SYS_IMMR 0xF0000000
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/* Where do the on board registers (CS4) live? */
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#define CONFIG_SYS_REGS_BASE 0xFA000000
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/*****************************************************************************
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*
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* You should not have to modify any of the following settings
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*
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*****************************************************************************/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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/*
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* Miscellaneous configurable options
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*/
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*/
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#if defined(CONFIG_SYS_SBC_BOOT_LOW)
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# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
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#else
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# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
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#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
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/* get the HRCW ISB field from CONFIG_SYS_IMMR */
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#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
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((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
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((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
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#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\
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HRCW_DPPC11 |\
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CONFIG_SYS_SBC_HRCW_IMMR |\
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HRCW_MMR00 |\
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HRCW_LBPC11 |\
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HRCW_APPC10 |\
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HRCW_CS10PC00 |\
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(CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
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CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
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/* no slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
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*/
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
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#ifndef CONFIG_SYS_RAMBOOT
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# define CONFIG_ENV_IS_IN_FLASH 1
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# ifdef CONFIG_ENV_IN_OWN_SECT
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
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# define CONFIG_ENV_SECT_SIZE 0x40000
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# else
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
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# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
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# endif /* CONFIG_ENV_IN_OWN_SECT */
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#else
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# define CONFIG_ENV_IS_IN_NVRAM 1
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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# define CONFIG_ENV_SIZE 0x200
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#endif /* CONFIG_SYS_RAMBOOT */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\
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/*HID0_DCE |*/\
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HID0_ICFI |\
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HID0_DCI |\
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HID0_IFEM |\
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HID0_ABE)
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#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
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HID0_IFEM |\
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HID0_ABE |\
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HID0_EMCP)
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#define CONFIG_SYS_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RMR 0
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_BCR (BCR_EBM |\
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BCR_PLDP |\
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BCR_EAV |\
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BCR_NPQM0)
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
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SIUMCR_APPC10 |\
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SIUMCR_CS10PC01)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
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SYPCR_BMT |\
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SYPCR_PBME |\
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SYPCR_LBME |\
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SYPCR_SWRI |\
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SYPCR_SWP)
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
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TMCNTSC_ALR |\
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TMCNTSC_TCF |\
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TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS |\
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PISCR_PTF |\
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PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
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* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
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* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
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* 3 unused
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* 4 60x GPCM 8 bit Board Regs, LEDs, switches
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* 5 unused
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* 6 unused
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* 7 unused
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* 8 PCMCIA
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* 9 unused
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* 10 unused
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* 11 unused
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*/
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/* Bank 0 - FLASH
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*
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_DECC_NONE |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_6_CLK |\
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ORxG_EHTR)
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/* Bank 1 - SDRAM
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*
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*/
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A8 |\
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ORxS_NUMR_12 |\
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ORxS_IBID)
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#define CONFIG_SYS_PSDMR 0x014DA412
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#define CONFIG_SYS_PSRT 0x79
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/* Bank 2 - SDRAM
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*
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*/
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#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
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BRx_PS_32 |\
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BRx_MS_SDRAM_L |\
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BRx_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A9 |\
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ORxS_NUMR_12)
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#define CONFIG_SYS_LSDMR 0x0169A512
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#define CONFIG_SYS_LSRT 0x79
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#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK)
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/* Bank 4 - On board registers
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*
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*/
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#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxG_TRLX)
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#endif /* __CONFIG_H */
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