upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Liu Gang 17b8614754 powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE ... When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>		11 years ago
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74xx_7xx	…
mpc5xx	…
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mpc8xx	…
mpc8xxx	powerpc/mpc8xxx: Add memory reset control	11 years ago
mpc83xx	…
mpc85xx	powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE	11 years ago
mpc86xx	powerpc/mpc8xxx: Add memory reset control	11 years ago
mpc512x	…
mpc824x	…
mpc8260	…
ppc4xx	…