upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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624 lines
16 KiB
624 lines
16 KiB
/*
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* Copyright (C) 2016 ARM Ltd.
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* based on the Allwinner H3 dtsi:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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memory {
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device_type = "memory";
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reg = <0x40000000 0>;
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x2000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: pll1_clk@1c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll6: pll6_clk@1c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2";
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};
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pll6d2: pll6d2_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll6 0>;
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clock-output-names = "pll6d2";
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};
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pll7: pll7_clk@1c2002c {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c2002c 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll7", "pll7x2";
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};
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cpu: cpu_clk@1c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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critical-clocks = <0>;
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};
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axi: axi_clk@1c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1: ahb1_clk@1c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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clock-output-names = "ahb1";
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};
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ahb2: ahb2_clk@1c2005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-h3-ahb2-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&ahb1>, <&pll6d2>;
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clock-output-names = "ahb2";
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};
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apb1: apb1_clk@1c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb2: apb2_clk@1c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
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clock-output-names = "apb2";
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};
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bus_gates: bus_gates_clk@1c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun50i-a64-bus-gates-clk",
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"allwinner,sunxi-multi-bus-gates-clk";
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reg = <0x01c20060 0x14>;
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ahb1_parent {
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clocks = <&ahb1>;
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clock-indices = <1>, <5>,
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<6>, <8>,
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<9>, <10>,
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<13>, <14>,
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<18>, <19>,
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<20>, <21>,
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<23>, <24>,
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<25>, <28>,
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<32>, <35>,
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<36>, <37>,
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<40>, <43>,
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<44>, <52>,
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<53>, <54>,
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<135>;
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clock-output-names = "bus_mipidsi", "bus_ce",
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"bus_dma", "bus_mmc0",
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"bus_mmc1", "bus_mmc2",
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"bus_nand", "bus_sdram",
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"bus_ts", "bus_hstimer",
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"bus_spi0", "bus_spi1",
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"bus_otg", "bus_otg_ehci0",
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"bus_ehci0", "bus_otg_ohci0",
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"bus_ve", "bus_lcd0",
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"bus_lcd1", "bus_deint",
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"bus_csi", "bus_hdmi",
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"bus_de", "bus_gpu",
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"bus_msgbox", "bus_spinlock",
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"bus_dbg";
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};
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ahb2_parent {
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clocks = <&ahb2>;
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clock-indices = <17>, <29>;
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clock-output-names = "bus_gmac", "bus_ohci0";
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};
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apb1_parent {
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clocks = <&apb1>;
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clock-indices = <64>, <65>,
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<69>, <72>,
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<76>, <77>,
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<78>;
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clock-output-names = "bus_codec", "bus_spdif",
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"bus_pio", "bus_ths",
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"bus_i2s0", "bus_i2s1",
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"bus_i2s2";
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};
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abp2_parent {
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clocks = <&apb2>;
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clock-indices = <96>, <97>,
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<98>, <101>,
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<112>, <113>,
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<114>, <115>,
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<116>;
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clock-output-names = "bus_i2c0", "bus_i2c1",
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"bus_i2c2", "bus_scr",
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"bus_uart0", "bus_uart1",
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"bus_uart2", "bus_uart3",
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"bus_uart4";
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};
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};
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mmc0_clk: mmc0_clk@1c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: mmc1_clk@1c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: mmc2_clk@1c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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clock-output-names = "mmc2";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc",
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"allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&bus_gates 8>, <&mmc0_clk>,
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<&mmc0_clk>, <&mmc0_clk>;
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clock-names = "ahb", "mmc",
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"output", "sample";
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resets = <&ahb_rst 8>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun50i-a64-mmc",
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"allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&bus_gates 9>, <&mmc1_clk>,
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<&mmc1_clk>, <&mmc1_clk>;
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clock-names = "ahb", "mmc",
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"output", "sample";
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resets = <&ahb_rst 9>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun50i-a64-mmc",
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"allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&bus_gates 10>, <&mmc2_clk>,
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<&mmc2_clk>, <&mmc2_clk>;
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clock-names = "ahb", "mmc",
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"output", "sample";
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resets = <&ahb_rst 10>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun50i-a64-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 69>;
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <2>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB8", "PB9";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart0_pins_b: uart0@1 {
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allwinner,pins = "PF2", "PF3";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart1_2pins: uart1_2@0 {
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allwinner,pins = "PG6", "PG7";
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allwinner,function = "uart1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart1_4pins: uart1_4@0 {
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allwinner,pins = "PG6", "PG7", "PG8", "PG9";
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allwinner,function = "uart1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart2_2pins: uart2_2@0 {
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allwinner,pins = "PB0", "PB1";
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allwinner,function = "uart2";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart2_4pins: uart2_4@0 {
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allwinner,pins = "PB0", "PB1", "PB2", "PB3";
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allwinner,function = "uart2";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_pins_a: uart3@0 {
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allwinner,pins = "PD0", "PD1";
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allwinner,function = "uart3";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_2pins_b: uart3_2@1 {
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allwinner,pins = "PH4", "PH5";
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allwinner,function = "uart3";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_4pins_b: uart3_4@1 {
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allwinner,pins = "PH4", "PH5", "PH6", "PH7";
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allwinner,function = "uart3";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart4_2pins: uart4_2@0 {
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allwinner,pins = "PD2", "PD3";
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allwinner,function = "uart4";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart4_4pins: uart4_4@0 {
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allwinner,pins = "PD2", "PD3", "PD4", "PD5";
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allwinner,function = "uart4";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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mmc0_pins: mmc0@0 {
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allwinner,pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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allwinner,function = "mmc0";
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allwinner,drive = <SUN4I_PINCTRL_30_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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mmc0_default_cd_pin: mmc0_cd_pin@0 {
|
|
allwinner,pins = "PF6";
|
|
allwinner,function = "gpio_in";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc1_pins: mmc1@0 {
|
|
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
"PG4", "PG5";
|
|
allwinner,function = "mmc1";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc2_pins: mmc2@0 {
|
|
allwinner,pins = "PC1", "PC5", "PC6", "PC8",
|
|
"PC9", "PC10";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c0_pins: i2c0_pins {
|
|
allwinner,pins = "PH0", "PH1";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c1_pins: i2c1_pins {
|
|
allwinner,pins = "PH2", "PH3";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c2_pins: i2c2_pins {
|
|
allwinner,pins = "PE14", "PE15";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
ahb_rst: reset@1c202c0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202c0 0xc>;
|
|
};
|
|
|
|
apb1_rst: reset@1c202d0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d0 0x4>;
|
|
};
|
|
|
|
apb2_rst: reset@1c202d8 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d8 0x4>;
|
|
};
|
|
|
|
uart0: serial@1c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 112>;
|
|
resets = <&apb2_rst 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 113>;
|
|
resets = <&apb2_rst 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 114>;
|
|
resets = <&apb2_rst 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 115>;
|
|
resets = <&apb2_rst 19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@1c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 116>;
|
|
resets = <&apb2_rst 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@1f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
i2c0: i2c@1c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bus_gates 96>;
|
|
resets = <&apb2_rst 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bus_gates 97>;
|
|
resets = <&apb2_rst 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@1c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bus_gates 98>;
|
|
resets = <&apb2_rst 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|