upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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318 lines
6.4 KiB
318 lines
6.4 KiB
/*
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* Device Tree Source for UniPhier PH1-LD4 SoC
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/include/ "uniphier-common32.dtsi"
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/ {
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compatible = "socionext,ph1-ld4";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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};
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clocks {
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <36864000>;
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};
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iobus_clk: iobus_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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};
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&soc {
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(512 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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port0x: gpio@55000008 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000008 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port1x: gpio@55000010 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000010 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port2x: gpio@55000018 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000018 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port3x: gpio@55000020 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000020 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port4: gpio@55000028 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000028 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port5x: gpio@55000030 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000030 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port6x: gpio@55000038 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000038 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port7x: gpio@55000040 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000040 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port8x: gpio@55000048 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000048 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port9x: gpio@55000050 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000050 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port10x: gpio@55000058 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000058 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port11x: gpio@55000060 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000060 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port12x: gpio@55000068 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000068 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port13x: gpio@55000070 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000070 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port14x: gpio@55000078 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000078 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port16x: gpio@55000088 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000088 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sdhc";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <0 76 4>;
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pinctrl-names = "default", "1.8v";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_1v8>;
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clocks = <&mio 0>;
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bus-width = <4>;
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};
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emmc: sdhc@5a500000 {
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compatible = "socionext,uniphier-sdhc";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <0 78 4>;
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pinctrl-names = "default", "1.8v";
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pinctrl-0 = <&pinctrl_emmc>;
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pinctrl-1 = <&pinctrl_emmc_1v8>;
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clocks = <&mio 1>;
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bus-width = <8>;
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non-removable;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&mio 3>, <&mio 6>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&mio 4>, <&mio 6>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 82 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&mio 5>, <&mio 6>;
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};
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};
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&refclk {
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clock-frequency = <24576000>;
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};
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&serial0 {
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clock-frequency = <36864000>;
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};
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&serial1 {
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clock-frequency = <36864000>;
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};
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&serial2 {
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clock-frequency = <36864000>;
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};
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&serial3 {
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interrupts = <0 29 4>;
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clock-frequency = <36864000>;
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};
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&mio {
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compatible = "socionext,ph1-ld4-mioctrl";
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clock-names = "stdmac", "ehci";
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clocks = <&sysctrl 10>, <&sysctrl 18>;
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};
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&peri {
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compatible = "socionext,ph1-ld4-perictrl";
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clock-names = "uart", "i2c";
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clocks = <&sysctrl 3>, <&sysctrl 4>;
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};
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&pinctrl {
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compatible = "socionext,ph1-ld4-pinctrl", "syscon";
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};
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&sysctrl {
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compatible = "socionext,ph1-ld4-sysctrl";
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};
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