upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
1.2 KiB
75 lines
1.2 KiB
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("Cannot get DRAM size: %d\n", ret);
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return ret;
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}
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debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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void lowlevel_init(void)
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{
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}
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static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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struct udevice *dev;
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for (uclass_first_device(UCLASS_CLK, &dev);
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dev;
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uclass_next_device(&dev)) {
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ulong rate;
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rate = clk_get_rate(dev);
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printf("%s: %lu\n", dev->name, rate);
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}
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return 0;
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}
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U_BOOT_CMD(
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clock, 2, 1, do_clock,
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"display information about clocks",
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""
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);
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