upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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228 lines
5.6 KiB
228 lines
5.6 KiB
/*
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* (C) Copyright 2016
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* Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
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*
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* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
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*
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* Copyright 2010 eXMeritus, A Boeing Company
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <mapmem.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct ccsr_gpio {
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u32 gpdir;
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u32 gpodr;
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u32 gpdat;
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u32 gpier;
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u32 gpimr;
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u32 gpicr;
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};
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struct mpc85xx_gpio_data {
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/* The bank's register base in memory */
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struct ccsr_gpio __iomem *base;
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/* The address of the registers; used to identify the bank */
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ulong addr;
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/* The GPIO count of the bank */
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uint gpio_count;
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/* The GPDAT register cannot be used to determine the value of output
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* pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
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* for output pins */
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u32 dat_shadow;
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};
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inline u32 gpio_mask(unsigned gpio) {
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return (1U << (31 - (gpio)));
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}
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static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpdat) & mask;
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}
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static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpdir) & mask;
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}
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static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
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{
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clrbits_be32(&base->gpdat, gpios);
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/* GPDIR register 0 -> input */
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clrbits_be32(&base->gpdir, gpios);
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}
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static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
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{
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clrbits_be32(&base->gpdat, gpios);
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/* GPDIR register 1 -> output */
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setbits_be32(&base->gpdir, gpios);
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}
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static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
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{
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setbits_be32(&base->gpdat, gpios);
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/* GPDIR register 1 -> output */
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setbits_be32(&base->gpdir, gpios);
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}
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static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
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{
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return in_be32(&base->gpodr) & mask;
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}
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static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
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gpios)
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{
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/* GPODR register 1 -> open drain on */
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setbits_be32(&base->gpodr, gpios);
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}
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static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
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u32 gpios)
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{
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/* GPODR register 0 -> open drain off (actively driven) */
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clrbits_be32(&base->gpodr, gpios);
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}
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static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
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return 0;
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}
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static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
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int value)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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if (value) {
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data->dat_shadow |= gpio_mask(gpio);
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mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
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} else {
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data->dat_shadow &= ~gpio_mask(gpio);
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mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
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}
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return 0;
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}
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static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
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int value)
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{
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return mpc85xx_gpio_set_value(dev, gpio, value);
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}
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static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
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/* Output -> use shadowed value */
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return !!(data->dat_shadow & gpio_mask(gpio));
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} else {
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/* Input -> read value from GPDAT register */
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return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
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}
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}
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static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
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}
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static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
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int value)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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if (value) {
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mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
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} else {
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mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
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}
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return 0;
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}
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static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
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{
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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int dir;
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dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
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return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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fdt_addr_t addr;
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fdt_size_t size;
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addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
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"reg", 0, &size);
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data->addr = addr;
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data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
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if (!data->base)
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return -ENOMEM;
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data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"ngpios", 32);
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data->dat_shadow = 0;
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return 0;
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}
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static int mpc85xx_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mpc85xx_gpio_data *data = dev_get_priv(dev);
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char name[32], *str;
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snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = data->gpio_count;
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return 0;
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}
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static const struct dm_gpio_ops gpio_mpc85xx_ops = {
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.direction_input = mpc85xx_gpio_direction_input,
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.direction_output = mpc85xx_gpio_direction_output,
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.get_value = mpc85xx_gpio_get_value,
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.set_value = mpc85xx_gpio_set_value,
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.get_open_drain = mpc85xx_gpio_get_open_drain,
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.set_open_drain = mpc85xx_gpio_set_open_drain,
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.get_function = mpc85xx_gpio_get_function,
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};
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static const struct udevice_id mpc85xx_gpio_ids[] = {
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{ .compatible = "fsl,pq3-gpio" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(gpio_mpc85xx) = {
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.name = "gpio_mpc85xx",
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.id = UCLASS_GPIO,
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.ops = &gpio_mpc85xx_ops,
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.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
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.of_match = mpc85xx_gpio_ids,
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.probe = mpc85xx_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
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};
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