upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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130 lines
3.4 KiB
130 lines
3.4 KiB
/*
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* Copyright (C) 2017 Microchip Corporation
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* Wenyou Yang <wenyou.yang@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <i2c.h>
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#include <nand.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5d2.h>
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#include <asm/arch/sama5d2_smc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_NAND_ATMEL
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static void board_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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at91_periph_clk_enable(ATMEL_ID_HSMC);
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/* Configure SMC CS3 for NAND */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
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AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
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AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */
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atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
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atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */
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atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */
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atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */
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atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */
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}
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#endif
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static void board_usb_hw_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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static void board_uart0_hw_init(void)
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{
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
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at91_periph_clk_enable(ATMEL_ID_UART0);
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}
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void board_debug_uart_init(void)
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{
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board_uart0_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND_ATMEL
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board_nand_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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board_usb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#define AT24MAC_MAC_OFFSET 0xfa
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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#ifdef CONFIG_I2C_EEPROM
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at91_set_ethaddr(AT24MAC_MAC_OFFSET);
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#endif
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return 0;
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}
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#endif
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