upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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219 lines
7.2 KiB
219 lines
7.2 KiB
/*------------------------------------------------------------------------------+
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* This source code is dual-licensed. You may use it under the terms of
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* the GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*-------------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------
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* Function: ext_bus_cntlr_init
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* Description: Initializes the External Bus Controller for the external
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* peripherals. IMPORTANT: For pass1 this code must run from
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* cache since you can not reliably change a peripheral banks
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* timing register (pbxap) while running code from that bank.
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* For ex., since we are running from ROM on bank 0, we can NOT
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* execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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* Bank 0 - Flash or Multi Purpose Socket
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* Bank 1 - Multi Purpose Socket or Flash
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* Bank 2 - not used
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* Bank 3 - not used
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* Bank 4 - not used
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* Bank 5 - not used
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* Bank 6 - used to switch on the 12V for the Multipurpose socket
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* Bank 7 - Config Register
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*-----------------------------------------------------------------------------*/
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#include <ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <configs/PIP405.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include "pip405.h"
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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mfdcr r3,CPC0_PSR /* get strapping reg */
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andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
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bnelr /* jump back if PCI boot */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 14; used to prefetch */
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mtctr r4 /* 14 cache lines to fit this function */
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/* in cache (gives us 8x14=112 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 14 cache lines */
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/*-------------------------------------------------------------------
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* Delay to ensure all accesses to ROM are complete before changing
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* bank 0 timings.
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*------------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*-----------------------------------------------------------------------
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* decide boot up mode
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*----------------------------------------------------------------------- */
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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mfdcr r4,EBC0_CFGDATA
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andi. r0, r4, 0x2000 /* mask out irrelevant bits */
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beq 0f /* jump if 8 bit bus width */
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/* setup 16 bit things
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*-----------------------------------------------------------------------
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* Memory Bank 0 (16 Bit Flash) initialization
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*---------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,(FLASH_AP_B)@h
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ori r4,r4,(FLASH_AP_B)@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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/* BS=0x010(4MB),BU=0x3(R/W), */
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addis r4,0,(FLASH_CR_B)@h
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ori r4,r4,(FLASH_CR_B)@l
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mtdcr EBC0_CFGDATA,r4
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b 1f
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0:
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/* 8Bit boot mode: */
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/*-----------------------------------------------------------------------
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* Memory Bank 0 Multi Purpose Socket initialization
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*----------------------------------------------------------------------- */
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/* 0x7F8FFE80 slowest boot */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,(MPS_AP_B)@h
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ori r4,r4,(MPS_AP_B)@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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/* BS=0x010(4MB),BU=0x3(R/W), */
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addis r4,0,(MPS_CR_B)@h
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ori r4,r4,(MPS_CR_B)@l
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mtdcr EBC0_CFGDATA,r4
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1:
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/*-----------------------------------------------------------------------
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* Memory Bank 2-3-4-5-6 (not used) initialization
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*-----------------------------------------------------------------------*/
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addi r4,0,PB1CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB2CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB3CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB4CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB5CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB6CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB7CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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nop /* pass2 DCR errata #8 */
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blr
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#if defined(CONFIG_BOOT_PCI)
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.section .bootpg,"ax"
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.globl _start_pci
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/*******************************************
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*/
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_start_pci:
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/* first handle errata #68 / PCI_18 */
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iccci r0, r0 /* invalidate I-cache */
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lis r31, 0
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mticcr r31 /* ICCR = 0 (all uncachable) */
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isync
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mfccr0 r28 /* set CCR0[24] = 1 */
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ori r28, r28, 0x0080
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mtccr0 r28
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/* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
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lis r28, 0xEF40
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addi r28, r28, 0x0004
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stw r31, 0x0C(r28) /* clear PMM0PCIHA */
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lis r29, 0xFFF8 /* open 512 kByte */
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addi r29, r29, 0x0001/* and enable this region */
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stwbrx r29, r0, r28 /* write PMM0MA */
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lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
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addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
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lis r31, 0x8000 /* set en bit bus 0 */
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ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
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stwbrx r31, r0, r28 /* write it */
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lwbrx r31, r0, r29 /* load XBCS register */
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oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
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stwbrx r31, r0, r29 /* write back XBCS register */
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nop
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nop
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b _start /* normal start */
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#endif
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