upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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307 lines
7.4 KiB
307 lines
7.4 KiB
/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.text
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#include <common.h>
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#include <config.h>
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#include <asm/macro.h>
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#include <generated/asm-offsets.h>
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/*
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* parameters for Synopsys DWC DDR2/DDR1 Memory Controller
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*/
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#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE)
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#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
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#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
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#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
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#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
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#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
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#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
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#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
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#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
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#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
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#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
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#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
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#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
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#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
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#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
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#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
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#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
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#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
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#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
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#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR)
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#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR
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#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2
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#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR
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#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR
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#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR
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#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR
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#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0
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#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0
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#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR
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#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR
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#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */
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/*
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* parameters for the ahbc controller
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*/
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#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
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#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
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#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
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/*
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* parameters for the ANDES PCU controller
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*/
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#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
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#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4
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/*
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* numeric 7 segment display
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*/
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.macro led, num
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write32 CONFIG_DEBUG_LED, \num
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.endm
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/*
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* Waiting for SDRAM to set up
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*/
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/*
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.macro wait_sdram
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li $r0, DDR2C_CSR_A
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1:
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lwi $r1, [$r0+FTSDMC021_CR2]
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bnez $r1, 1b
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.endm
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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.globl lowlevel_init
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lowlevel_init:
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move $r10, $lp
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/* U200 */
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! led 0x00
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! jal scale_to_500mhz
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led 0x10
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jal mem_init
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led 0x20
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jal remap
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
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led 0x2f
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jal enable_fpu
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#endif
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led 0x30
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ret $r10
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scale_to_500mhz:
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move $r11, $lp
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/*
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* scale to 500Mhz
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*/
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led 0x01
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write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4
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move $lp, $r11
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ret
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mem_init:
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move $r11, $lp
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/*
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* config AHB Controller
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*/
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led 0x12
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write32 AHBC_BSR6_A, AHBC_BSR6_D
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/*
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* config Synopsys DWC DDR2/DDR1 Memory Controller
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*/
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ddr2c_init:
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set_dcr:
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led 0x14
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write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4
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auto_sizing:
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/*
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* ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
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*/
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set_iocr:
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led 0x19
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write32 DDR2C_IOCR_A, DDR2C_IOCR_D
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set_drr:
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led 0x16
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write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812
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set_dllcr:
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led 0x18
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write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
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write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
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set_rslr0:
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write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040
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set_rdgr0:
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write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf
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set_dtar:
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led 0x15
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write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000
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set_mode:
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led 0x17
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write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852
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set_ccr:
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write32 DDR2C_CCR_A, DDR2C_CCR_D
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#ifdef TRIGGER_INIT:
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trigger_init:
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write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000
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/* Wait for ddr init state to be set */
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msync ALL
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isb
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/* Wait until the config initialization is finish */
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1:
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la $r4, DDR2C_CSR_A
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lwi $r5, [$r4]
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srli $r5, $r5, 23
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bnez $r5, 1b
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#endif
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data_training:
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! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004
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/* Wait for ddr init state to be set */
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msync ALL
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isb
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/* wait until the ddr data trainning is complete */
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1:
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la $r4, DDR2C_CSR_A
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lwi $r5, [$r4]
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srli $r6, $r5, 23
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bnez $r6, 1b
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lwi $r1, [$r4]
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srli $r6, $r5, 20
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li $r5, 0x00ffffff
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swi $r1, [$r4]
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bnez $r6, ddr2c_init
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led 0x1a
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move $lp, $r11
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ret
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remap:
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move $r11, $lp
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#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
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bal 2f
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relo_base:
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move $r0, $lp
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#else
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relo_base:
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mfusr $r0, $pc
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#endif /* __NDS32_N1213_43U1H__ */
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/*
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* Remapping
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*/
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#ifdef CONFIG_MEM_REMAP
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/*
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* Copy ROM code to SDRAM base for memory remap layout.
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* This is not the real relocation, the real relocation is the function
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* relocate_code() is start.S which supports the systems is memory
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* remapped or not.
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*/
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/*
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* Doing memory remap is essential for preparing some non-OS or RTOS
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* applications.
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*
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* This is also a must on ADP-AG101 board.
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* The reason is because the ROM/FLASH circuit on PCB board.
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* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
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* ROM/FLASH is used to boot.
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*
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* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
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* and the FLASH is connected to BANK1.
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* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
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* and the FLASH is connected to BANK0.
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* It will occur problem when doing flash probing if the flash is at
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* BANK0 (0x00000000) while memory remapping was skipped.
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*
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* Other board like ADP-AG101P may not enable this since there is only
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* a FLASH connected to bank0.
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*/
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led 0x21
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li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
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li $r5, 0x0
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la $r1, relo_base /* get $pc or $lp */
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sub $r2, $r0, $r1
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sethi $r6, hi20(_end)
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ori $r6, $r6, lo12(_end)
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add $r6, $r6, $r2
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1:
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lwi.p $r7, [$r5], #4
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swi.p $r7, [$r4], #4
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blt $r5, $r6, 1b
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/* set remap bit */
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/*
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* MEM remap bit is operational
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* - use it to map writeable memory at 0x00000000, in place of flash
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* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
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* - after remap: flash/rom 0x80000000, sdram: 0x00000000
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*/
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led 0x2c
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setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
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#endif /* #ifdef CONFIG_MEM_REMAP */
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move $lp, $r11
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2:
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ret
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/*
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* enable_fpu:
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* Some of Andes CPU version support FPU coprocessor, if so,
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* and toolchain support FPU instruction set, we should enable it.
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*/
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
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enable_fpu:
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mfsr $r0, $CPU_VER /* enable FPU if it exists */
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srli $r0, $r0, 3
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andi $r0, $r0, 1
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beqz $r0, 1f /* skip if no COP */
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mfsr $r0, $FUCOP_EXIST
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srli $r0, $r0, 31
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beqz $r0, 1f /* skip if no FPU */
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mfsr $r0, $FUCOP_CTL
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ori $r0, $r0, 1
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mtsr $r0, $FUCOP_CTL
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1:
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ret
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#endif
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.globl show_led
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show_led:
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li $r8, (CONFIG_DEBUG_LED)
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swi $r7, [$r8]
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ret
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#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
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