upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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51 lines
1.5 KiB
51 lines
1.5 KiB
/*
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* (C) Copyright 2008
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*
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* Georg Schardt <schardt@team-ctech.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* CAUTION: This file is based on the xparameters.h automatically
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* generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
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*/
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#ifndef __XPARAMETER_H__
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#define __XPARAMETER_H__
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/* RS232 */
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#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
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#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
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/* INT_C */
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#define XPAR_XPS_INTC_0_DEVICE_ID 0
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#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
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/* CPU core clock */
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#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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/* RAM */
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#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
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/* FLASH */
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#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
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#endif
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