upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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250 lines
6.0 KiB
250 lines
6.0 KiB
/*
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* (C) Copyright 2003
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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int board_early_init_f (void)
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{
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out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
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out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0)
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* IRQ 26 (EXT IRQ 1)
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* IRQ 27 (EXT IRQ 2)
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* IRQ 28 (EXT IRQ 3)
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* IRQ 29 (EXT IRQ 4)
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* IRQ 30 (EXT IRQ 5)
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* IRQ 31 (EXT IRQ 6)
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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#if 1 /* test-only */
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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#else
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mtebc (epcr, 0x28400000); /* ebc in high-z */
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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int misc_init_r (void)
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{
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/* adjust flash start and size as well as the offset */
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gd->bd->bi_flashstart = 0 - flash_info[0].size;
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gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
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#if 0
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
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volatile unsigned char *duart0_mcr =
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(unsigned char *)((ulong)DUART0_BA + 4);
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volatile unsigned char *duart1_mcr =
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(unsigned char *)((ulong)DUART1_BA + 4);
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bd_t *bd = gd->bd;
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char * tmp; /* Temporary char pointer */
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned long cntrl0Reg;
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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#endif
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#if 0
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/*
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* Enable power on PS/2 interface
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*/
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*fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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*duart0_mcr = 0x08;
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*duart1_mcr = 0x08;
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#endif
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming PPChameleonEVB");
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} else {
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puts(str);
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}
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_CFB_CONSOLE
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# ifdef CONFIG_CONSOLE_EXTRA_INFO
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# include <video_fb.h>
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extern GraphicDevice smi;
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void video_get_info_str (int line_number, char *info)
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{
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uint pvr = get_pvr ();
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/* init video info strings for graphic console */
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switch (line_number) {
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case 1:
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switch (pvr) {
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case PVR_405EP_RB:
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sprintf (info, " AMCC PowerPC 405EP Rev. B");
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break;
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default:
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sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
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break;
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}
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return;
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case 2:
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sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
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return;
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case 3:
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sprintf (info, " %s", smi.modeIdent);
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return;
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}
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/* no more info lines */
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*info = 0;
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return;
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}
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# endif /* CONFIG_CONSOLE_EXTRA_INFO */
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#endif /* CONFIG_CFB_CONSOLE */
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