upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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793 lines
18 KiB
793 lines
18 KiB
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void __ft_board_setup(void *blob, bd_t *bd);
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#undef FPGA_DEBUG
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] =
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{
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#if defined(CONFIG_CPCI405_VER2)
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# if defined(CONFIG_CPCI405AB)
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# include "fpgadata_cpci405ab.c"
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# else
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# include "fpgadata_cpci4052.c"
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# endif
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#else
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# include "fpgadata_cpci405.c"
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#endif
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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#include "../common/auto_update.h"
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#if defined(CONFIG_CPCI405AB)
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au_image_t au_image[] = {
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{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
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{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
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{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
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{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
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{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
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};
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#else
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#if defined(CONFIG_CPCI405_VER2)
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au_image_t au_image[] = {
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{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
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{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
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{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
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{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
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{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
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};
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#else
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au_image_t au_image[] = {
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{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
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{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
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{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
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{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
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{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
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};
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#endif
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#endif
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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/* Prototypes */
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int cpci405_version(void);
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int gunzip(void *, int, unsigned char *, unsigned long *);
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void lxt971_no_sleep(void);
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int board_early_init_f(void)
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{
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#ifndef CONFIG_CPCI405_VER2
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int index, len, i;
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int status;
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#endif
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#ifdef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void)get_clocks();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init();
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console_init_f();
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#endif
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/*
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* First pull fpga-prg pin low,
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* to disable fpga logic (on version 2 board)
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*/
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out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
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out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
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out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
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out_be32((void *)GPIO0_OR, 0); /* pull prg low */
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/*
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* Boot onboard FPGA
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*/
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#ifndef CONFIG_CPCI405_VER2
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if (cpci405_version() == 1) {
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status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void)get_clocks();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init();
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console_init_f();
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#endif
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after "
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"asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after "
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"deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after "
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"programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index = 0; index < 1000; index++)
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udelay(1000);
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}
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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}
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#endif /* !CONFIG_CPCI405_VER2 */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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#if defined(CONFIG_CPCI405_6U)
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if (cpci405_version() == 3) {
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mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
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} else {
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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}
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#else
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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#endif
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,
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* INT0 highest priority */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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int ctermm2(void)
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{
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#if defined(CONFIG_CPCI405_VER2)
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return 0; /* no, board is cpci405 */
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#else
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if ((in_8((void*)0xf0000400) == 0x00) &&
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(in_8((void*)0xf0000401) == 0x01))
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return 0; /* no, board is cpci405 */
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else
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return -1; /* yes, board is cterm-m2 */
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#endif
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}
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int cpci405_host(void)
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{
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if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
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return -1; /* yes, board is cpci405 host */
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else
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return 0; /* no, board is cpci405 adapter */
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}
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int cpci405_version(void)
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{
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unsigned long cntrl0Reg;
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unsigned long value;
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/*
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* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x03000000);
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out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
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udelay(1000); /* wait some time before reading input */
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value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
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/*
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* Restore GPIO settings
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*/
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mtdcr(cntrl0, cntrl0Reg);
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switch (value) {
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case 0x00180000:
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/* CS2==1 && CS3==1 -> version 1 */
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return 1;
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case 0x00080000:
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/* CS2==0 && CS3==1 -> version 2 */
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return 2;
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case 0x00100000:
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/* CS2==1 && CS3==0 -> version 3 or 6U board */
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return 3;
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case 0x00000000:
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/* CS2==0 && CS3==0 -> version 4 */
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return 4;
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default:
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/* should not be reached! */
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return 2;
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}
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}
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int misc_init_r (void)
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{
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unsigned long cntrl0Reg;
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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#if defined(CONFIG_CPCI405_VER2)
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{
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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/*
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* On CPCI-405 version 2 the environment is saved in eeprom!
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* FPGA can be gzip compressed (malloc) and booted this late.
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*/
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if (cpci405_version() >= 2) {
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x00300000);
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
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(uchar *)fpgadata, &len) != 0) {
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printf("GUNZIP ERROR - must RESET board to recover\n");
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do_reset(NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after "
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"asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after "
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"deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after "
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"programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index + 1]));
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index += len + 3;
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}
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putc('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay(1000);
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}
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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/* restore gpio/cs settings */
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mtdcr(cntrl0, cntrl0Reg);
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index + 1]));
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index += len + 3;
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}
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putc('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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#if defined(CONFIG_CPCI405_6U)
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#error HIER GETH ES WEITER MIT IO ACCESSORS
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if (cpci405_version() == 3) {
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/*
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* Enable outputs in fpga on version 3 board
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*/
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
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CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
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/*
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* Set outputs to 0
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*/
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out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
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/*
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* Reset external DUART
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*/
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
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CONFIG_SYS_FPGA_MODE_DUART_RESET);
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udelay(100);
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
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~CONFIG_SYS_FPGA_MODE_DUART_RESET);
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}
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#endif
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}
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else {
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puts("\n*** U-Boot Version does not match Board Version!\n");
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puts("*** CPCI-405 Version 1.x detected!\n");
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puts("*** Please use correct U-Boot version "
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"(CPCI405 instead of CPCI4052)!\n\n");
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}
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}
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#else /* CONFIG_CPCI405_VER2 */
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if (cpci405_version() >= 2) {
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puts("\n*** U-Boot Version does not match Board Version!\n");
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puts("*** CPCI-405 Board Version 2.x detected!\n");
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puts("*** Please use correct U-Boot version "
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"(CPCI4052 instead of CPCI405)!\n\n");
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}
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#endif /* CONFIG_CPCI405_VER2 */
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/*
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* Select cts (and not dsr) on uart1
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x00001000);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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#ifndef CONFIG_CPCI405_VER2
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int index;
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int len;
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#endif
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char str[64];
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int i = getenv_r("serial#", str, sizeof(str));
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unsigned short ver;
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puts("Board: ");
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if (i == -1)
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puts("### No HW ID - assuming CPCI405");
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else
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puts(str);
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ver = cpci405_version();
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printf(" (Ver %d.x, ", ver);
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if (ctermm2()) {
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char str[4];
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/*
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* Read board-id and save in env-variable
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*/
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sprintf(str, "%d", *(unsigned char *)0xf0000400);
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setenv("boardid", str);
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printf("CTERM-M2 - Id=%s)", str);
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} else {
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if (cpci405_host())
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puts("PCI Host Version)");
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else
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puts("PCI Adapter Version)");
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}
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#ifndef CONFIG_CPCI405_VER2
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puts("\nFPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf("%s ", &(fpgadata[index + 1]));
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index += len + 3;
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}
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#endif
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putc('\n');
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return 0;
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}
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void reset_phy(void)
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{
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#if defined(CONFIG_LXT971_NO_SLEEP)
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
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void ide_set_reset(int on)
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{
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
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~CONFIG_SYS_FPGA_MODE_CF_RESET);
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} else { /* release RESET */
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out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
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in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
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CONFIG_SYS_FPGA_MODE_CF_RESET);
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}
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}
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#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
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#if defined(CONFIG_PCI)
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void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char int_line = 0xff;
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/*
|
|
* Write pci interrupt line register (cpci405 specific)
|
|
*/
|
|
switch (PCI_DEV(dev) & 0x03) {
|
|
case 0:
|
|
int_line = 27 + 2;
|
|
break;
|
|
case 1:
|
|
int_line = 27 + 3;
|
|
break;
|
|
case 2:
|
|
int_line = 27 + 0;
|
|
break;
|
|
case 3:
|
|
int_line = 27 + 1;
|
|
break;
|
|
}
|
|
|
|
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
|
}
|
|
|
|
int pci_pre_init(struct pci_controller *hose)
|
|
{
|
|
hose->fixup_irq = cpci405_pci_fixup_irq;
|
|
return 1;
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
int rc;
|
|
|
|
__ft_board_setup(blob, bd);
|
|
|
|
/*
|
|
* Disable PCI in adapter mode.
|
|
*/
|
|
if (!cpci405_host()) {
|
|
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
|
|
"disabled", sizeof("disabled"), 1);
|
|
if (rc) {
|
|
printf("Unable to update property status in PCI node, "
|
|
"err=%s\n",
|
|
fdt_strerror(rc));
|
|
}
|
|
}
|
|
}
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
|
|
|
#if defined(CONFIG_CPCI405AB)
|
|
#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
CONFIG_SYS_FPGA_MODE), \
|
|
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
CONFIG_SYS_FPGA_MODE)) | \
|
|
CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
|
|
|
|
#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
CONFIG_SYS_FPGA_MODE), \
|
|
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
CONFIG_SYS_FPGA_MODE)) & \
|
|
~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
|
|
|
|
#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
|
|
CONFIG_SYS_FPGA_STATUS)) & \
|
|
CONFIG_SYS_FPGA_MODE_1WIRE)
|
|
|
|
/*
|
|
* Generate a 1-wire reset, return 1 if no presence detect was found,
|
|
* return 0 otherwise.
|
|
* (NOTE: Does not handle alarm presence from DS2404/DS1994)
|
|
*/
|
|
int OWTouchReset(void)
|
|
{
|
|
int result;
|
|
|
|
ONE_WIRE_CLEAR;
|
|
udelay(480);
|
|
ONE_WIRE_SET;
|
|
udelay(70);
|
|
|
|
result = ONE_WIRE_GET;
|
|
|
|
udelay(410);
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* Send 1 a 1-wire write bit.
|
|
* Provide 10us recovery time.
|
|
*/
|
|
void OWWriteBit(int bit)
|
|
{
|
|
if (bit) {
|
|
/*
|
|
* write '1' bit
|
|
*/
|
|
ONE_WIRE_CLEAR;
|
|
udelay(6);
|
|
ONE_WIRE_SET;
|
|
udelay(64);
|
|
} else {
|
|
/*
|
|
* write '0' bit
|
|
*/
|
|
ONE_WIRE_CLEAR;
|
|
udelay(60);
|
|
ONE_WIRE_SET;
|
|
udelay(10);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Read a bit from the 1-wire bus and return it.
|
|
* Provide 10us recovery time.
|
|
*/
|
|
int OWReadBit(void)
|
|
{
|
|
int result;
|
|
|
|
ONE_WIRE_CLEAR;
|
|
udelay(6);
|
|
ONE_WIRE_SET;
|
|
udelay(9);
|
|
|
|
result = ONE_WIRE_GET;
|
|
|
|
udelay(55);
|
|
return result;
|
|
}
|
|
|
|
void OWWriteByte(int data)
|
|
{
|
|
int loop;
|
|
|
|
for (loop = 0; loop < 8; loop++) {
|
|
OWWriteBit(data & 0x01);
|
|
data >>= 1;
|
|
}
|
|
}
|
|
|
|
int OWReadByte(void)
|
|
{
|
|
int loop, result = 0;
|
|
|
|
for (loop = 0; loop < 8; loop++) {
|
|
result >>= 1;
|
|
if (OWReadBit())
|
|
result |= 0x80;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
unsigned short val;
|
|
int result;
|
|
int i;
|
|
unsigned char ow_id[6];
|
|
char str[32];
|
|
unsigned char ow_crc;
|
|
|
|
/*
|
|
* Clear 1-wire bit (open drain with pull-up)
|
|
*/
|
|
val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
|
|
CONFIG_SYS_FPGA_MODE));
|
|
val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
|
|
out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
|
|
CONFIG_SYS_FPGA_MODE), val);
|
|
|
|
result = OWTouchReset();
|
|
if (result != 0)
|
|
puts("No 1-wire device detected!\n");
|
|
|
|
OWWriteByte(0x33); /* send read rom command */
|
|
OWReadByte(); /* skip family code ( == 0x01) */
|
|
for (i = 0; i < 6; i++)
|
|
ow_id[i] = OWReadByte();
|
|
ow_crc = OWReadByte(); /* read crc */
|
|
|
|
sprintf(str, "%08X%04X",
|
|
*(unsigned int *)&ow_id[0],
|
|
*(unsigned short *)&ow_id[4]);
|
|
printf("Setting environment variable 'ow_id' to %s\n", str);
|
|
setenv("ow_id", str);
|
|
|
|
return 0;
|
|
}
|
|
U_BOOT_CMD(
|
|
onewire, 1, 1, do_onewire,
|
|
"Read 1-write ID",
|
|
NULL
|
|
);
|
|
|
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
|
|
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
|
|
|
|
/*
|
|
* Write backplane ip-address...
|
|
*/
|
|
int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
bd_t *bd = gd->bd;
|
|
char *buf;
|
|
ulong crc;
|
|
char str[32];
|
|
char *ptr;
|
|
IPaddr_t ipaddr;
|
|
|
|
buf = malloc(CONFIG_ENV_SIZE_2);
|
|
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
|
|
(uchar *)buf, CONFIG_ENV_SIZE_2))
|
|
puts("\nError reading backplane EEPROM!\n");
|
|
else {
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
|
|
if (crc != *(ulong *)buf) {
|
|
printf("ERROR: crc mismatch %08lx %08lx\n",
|
|
crc, *(ulong *)buf);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Find bp_ip
|
|
*/
|
|
ptr = strstr(buf+4, "bp_ip=");
|
|
if (ptr == NULL) {
|
|
printf("ERROR: bp_ip not found!\n");
|
|
return -1;
|
|
}
|
|
ptr += 6;
|
|
ipaddr = string_to_ip(ptr);
|
|
|
|
/*
|
|
* Update whole ip-addr
|
|
*/
|
|
bd->bi_ip_addr = ipaddr;
|
|
sprintf(str, "%ld.%ld.%ld.%ld",
|
|
(bd->bi_ip_addr & 0xff000000) >> 24,
|
|
(bd->bi_ip_addr & 0x00ff0000) >> 16,
|
|
(bd->bi_ip_addr & 0x0000ff00) >> 8,
|
|
(bd->bi_ip_addr & 0x000000ff));
|
|
setenv("ipaddr", str);
|
|
printf("Updated ip_addr from bp_eeprom to %s!\n", str);
|
|
}
|
|
|
|
free(buf);
|
|
|
|
return 0;
|
|
}
|
|
U_BOOT_CMD(
|
|
getbpip, 1, 1, do_get_bpip,
|
|
"Update IP-Address with Backplane IP-Address",
|
|
NULL
|
|
);
|
|
|
|
/*
|
|
* Set and print backplane ip...
|
|
*/
|
|
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
char *buf;
|
|
char str[32];
|
|
ulong crc;
|
|
|
|
if (argc < 2) {
|
|
puts("ERROR!\n");
|
|
return -1;
|
|
}
|
|
|
|
printf("Setting bp_ip to %s\n", argv[1]);
|
|
buf = malloc(CONFIG_ENV_SIZE_2);
|
|
memset(buf, 0, CONFIG_ENV_SIZE_2);
|
|
sprintf(str, "bp_ip=%s", argv[1]);
|
|
strcpy(buf+4, str);
|
|
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
|
|
*(ulong *)buf = crc;
|
|
|
|
if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
|
|
0, (uchar *)buf, CONFIG_ENV_SIZE_2))
|
|
puts("\nError writing backplane EEPROM!\n");
|
|
|
|
free(buf);
|
|
|
|
return 0;
|
|
}
|
|
U_BOOT_CMD(
|
|
setbpip, 2, 1, do_set_bpip,
|
|
"Write Backplane IP-Address",
|
|
NULL
|
|
);
|
|
|
|
#endif /* CONFIG_CPCI405AB */
|
|
|