upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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85 lines
1.9 KiB
85 lines
1.9 KiB
/*
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* (C) Copyright 2004
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* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
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*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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#include <netdev.h>
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int checkboard (void)
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{
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/*TODO: Check processor type */
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puts ( "Board: Hidden Dragon "
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#ifdef CONFIG_MPC8240
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"8240"
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#endif
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#ifdef CONFIG_MPC8245
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"8245"
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#endif
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" ##Test not implemented yet##\n");
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/* TODO: Implement board test */
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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long size;
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long new_bank0_end;
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long mear1;
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long emear1;
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size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
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new_bank0_end = size - 1;
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mear1 = mpc824x_mpc107_getreg(MEAR1);
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emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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return (size);
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_hidden_dragon_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_hidden_dragon_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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