upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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408 lines
12 KiB
408 lines
12 KiB
/*
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* (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/io.h>
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#include <asm/immap_8260.h>
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int hwc_flash_size (void);
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int hwc_local_sdram_size (void);
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int hwc_main_sdram_size (void);
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int hwc_serial_number (void);
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int hwc_mac_address (char *str);
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int hwc_manufact_date (char *str);
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int seeprom_read (int addr, uchar * data, int size);
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*
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* The port definitions are taken from the old firmware (see
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* also SYS/H/4539.H):
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*
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* ppar psor pdir podr pdat
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* PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0
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* PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290
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* PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d
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* PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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{0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */
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{0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */
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{0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */
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{0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */
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{0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */
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{0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */
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{0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */
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{0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */
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{0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */
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{0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */
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{0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */
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{0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */
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{0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */
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{0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */
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{0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */
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{0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */
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{0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */
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{0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */
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{0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */
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{0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */
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{0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */
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{0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */
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{0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */
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{0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */
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{0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */
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{0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */
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{0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */
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{0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */
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{0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */
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{0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */
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{0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */
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{0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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{0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */
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{0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */
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{0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */
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{0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */
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{0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */
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{0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */
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{0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */
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{0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */
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{0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */
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{0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */
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{0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */
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{0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */
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{0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */
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{0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */
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{1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */
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{1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */
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{1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */
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{1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */
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{1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */
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{1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */
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{1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */
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{1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */
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{1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */
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{1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */
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{1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */
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{1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */
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{1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */
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{1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */
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{0, 0, 0, 0, 0, 0}, /* PB3 */
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{0, 0, 0, 0, 0, 0}, /* PB2 */
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{0, 0, 0, 0, 0, 0}, /* PB1 */
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{0, 0, 0, 0, 0, 0}, /* PB0 */
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},
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/* Port C configuration */
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{ /* conf ppar psor pdir podr pdat */
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{0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */
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{0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */
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{0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */
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{0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */
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{0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */
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{0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */
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{0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */
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{1, 0, 0, 1, 0, 0}, /* PC24 MDIO */
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{1, 0, 0, 1, 0, 0}, /* PC23 MDC */
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{0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */
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{0, 0, 0, 1, 0, 0}, /* PC21 */
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{0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */
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{0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */
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{1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */
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{0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */
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{1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */
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{0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */
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{0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */
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{0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */
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{0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */
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{0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */
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{0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */
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{0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */
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{0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */
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{0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */
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{0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */
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{0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */
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{0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */
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{0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */
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{0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */
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{0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */
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{0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */
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},
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/* Port D configuration */
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{ /* conf ppar psor pdir podr pdat */
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{0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */
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{0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */
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{0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */
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{0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */
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{0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */
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{0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */
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{0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */
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{0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */
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{1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */
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{0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */
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{0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */
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{0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */
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{0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */
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{0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */
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{0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */
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{0, 0, 0, 1, 0, 0}, /* PD16 */
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{0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */
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{0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */
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{0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */
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{0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */
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{0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */
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{0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */
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{1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */
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{1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */
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{0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */
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{0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */
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{0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */
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{0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */
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{0, 0, 0, 0, 0, 0}, /* PD3 */
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{0, 0, 0, 0, 0, 0}, /* PD2 */
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{0, 0, 0, 0, 0, 0}, /* PD1 */
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{0, 0, 0, 0, 0, 0}, /* PD0 */
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}
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};
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar *base;
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ulong maxsize;
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int i;
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memctl->memc_psrt = CONFIG_SYS_PSRT;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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#ifndef CONFIG_SYS_RAMBOOT
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immap->im_siu_conf.sc_ppc_acr = 0x00000026;
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immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
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immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
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immap->im_siu_conf.sc_lcl_acr = 0x00000000;
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immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
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immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
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immap->im_siu_conf.sc_tescr1 = 0x00004000;
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immap->im_siu_conf.sc_ltescr1 = 0x00004000;
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/* Init Main SDRAM */
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#define OP_VALUE 0x404A241A
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#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
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base = (uchar *) CONFIG_SYS_SDRAM_BASE;
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memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
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*base = 0xFF;
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memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
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for (i = 0; i < 8; i++)
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*base = 0xFF;
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memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
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*(base + 0x110) = 0xFF;
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memctl->memc_psdmr = OP_VALUE;
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memctl->memc_lsdmr = 0x4086A522;
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*base = 0xFF;
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/* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be
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* mapped by the controller. That means, that the initial mapping has
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* to be (at least) twice as large as the maximum expected size.
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*/
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maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
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maxsize = get_ram_size((long *)base, maxsize);
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memctl->memc_or1 |= ~(maxsize - 1);
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if (maxsize != hwc_main_sdram_size ())
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printf ("Oops: memory test has not found all memory!\n");
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#endif
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icache_enable ();
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/* return total ram size of SDRAM */
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return (maxsize);
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}
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int checkboard (void)
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{
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char string[32];
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hwc_manufact_date (string);
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printf ("Board: Interphase 4539 (#%d %s)\n",
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hwc_serial_number (),
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string);
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#ifdef DEBUG
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printf ("Manufacturing date: %s\n", string);
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printf ("Serial number : %d\n", hwc_serial_number ());
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printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20);
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printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20);
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printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20);
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hwc_mac_address (string);
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printf ("MAC address : %s\n", string);
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#endif
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return 0;
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}
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int misc_init_r (void)
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{
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char *s, str[32];
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int num;
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if ((s = getenv ("serial#")) == NULL &&
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(num = hwc_serial_number ()) != -1) {
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sprintf (str, "%06d", num);
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setenv ("serial#", str);
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}
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if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
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setenv ("ethaddr", str);
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}
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return (0);
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}
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/***************************************************************
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* We take some basic Hardware Configuration Parameter from the
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* Serial EEPROM conected to the PSpan bridge. We keep it as
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* simple as possible.
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*/
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int hwc_flash_size (void)
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{
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uchar byte;
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if (!seeprom_read (0x40, &byte, sizeof (byte))) {
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switch ((byte >> 2) & 0x3) {
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case 0x1:
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return 0x0400000;
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break;
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case 0x2:
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return 0x0800000;
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break;
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case 0x3:
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return 0x1000000;
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default:
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return 0x0100000;
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}
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}
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return -1;
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}
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int hwc_local_sdram_size (void)
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{
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uchar byte;
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if (!seeprom_read (0x40, &byte, sizeof (byte))) {
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switch ((byte & 0x03)) {
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case 0x1:
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return 0x0800000;
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case 0x2:
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return 0x1000000;
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default:
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return 0; /* not present */
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}
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}
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return -1;
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}
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int hwc_main_sdram_size (void)
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{
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uchar byte;
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if (!seeprom_read (0x41, &byte, sizeof (byte))) {
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return 0x1000000 << ((byte >> 5) & 0x7);
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}
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return -1;
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}
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int hwc_serial_number (void)
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{
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int sn = -1;
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if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
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sn = cpu_to_le32 (sn);
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}
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return sn;
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}
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int hwc_mac_address (char *str)
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{
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char mac[6];
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if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
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sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
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mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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} else {
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strcpy (str, "ERROR");
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return -1;
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}
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return 0;
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}
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int hwc_manufact_date (char *str)
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{
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uchar byte;
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int value;
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if (seeprom_read (0x92, &byte, sizeof (byte)))
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goto out;
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value = byte;
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if (seeprom_read (0x93, &byte, sizeof (byte)))
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goto out;
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value += byte << 8;
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sprintf (str, "%02d/%02d/%04d",
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value & 0x1F, (value >> 5) & 0xF,
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1980 + ((value >> 9) & 0x1FF));
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return 0;
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out:
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strcpy (str, "ERROR");
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return -1;
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}
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#define PSPAN_ADDR 0xF0020000
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#define EEPROM_REG 0x408
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#define EEPROM_READ_CMD 0xA000
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#define PSPAN_WRITE(a,v) \
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*((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
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#define PSPAN_READ(a) \
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*((volatile unsigned long *)(PSPAN_ADDR+(a)))
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int seeprom_read (int addr, uchar * data, int size)
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{
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ulong val, cmd;
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int i;
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for (i = 0; i < size; i++) {
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cmd = EEPROM_READ_CMD;
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cmd |= ((addr + i) << 24) & 0xff000000;
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/* Wait for ACT to authorize write */
|
|
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
|
eieio ();
|
|
|
|
/* Write command */
|
|
PSPAN_WRITE (EEPROM_REG, cmd);
|
|
|
|
/* Wait for data to be valid */
|
|
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
|
eieio ();
|
|
/* Do it twice, first read might be erratic */
|
|
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
|
eieio ();
|
|
|
|
/* Read error */
|
|
if (val & 0x00000040) {
|
|
return -1;
|
|
} else {
|
|
data[i] = (val >> 16) & 0xff;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|