upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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227 lines
6.0 KiB
227 lines
6.0 KiB
/*
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* Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
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* Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/global_data.h>
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#include <pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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static struct pci_controller pci_hose;
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/**************************************************************************
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* pci_init_board()
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*
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*/
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void
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pci_init_board(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile law512x_t *pci_law;
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volatile pot512x_t *pci_pot;
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volatile pcictrl512x_t *pci_ctrl;
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volatile pciconf512x_t *pci_conf;
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u16 reg16;
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u32 reg32;
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u32 dev;
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int i;
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struct pci_controller *hose;
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/* Set PCI divider for 33MHz */
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reg32 = in_be32(&im->clk.scfr[0]);
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reg32 &= ~(SCFR1_PCI_DIV_MASK);
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reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
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out_be32(&im->clk.scfr[0], reg32);
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clrsetbits_be32(&im->clk.scfr[0],
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SCFR1_PCI_DIV_MASK,
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SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
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);
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pci_law = im->sysconf.pcilaw;
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pci_pot = im->ios.pot;
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pci_ctrl = &im->pci_ctrl;
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pci_conf = &im->pci_conf;
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hose = &pci_hose;
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/*
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* Release PCI RST Output signal
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*/
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out_be32(&pci_ctrl->gcr, 0);
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udelay(2000);
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out_be32(&pci_ctrl->gcr, 1);
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/* We need to wait at least a 1sec based on PCI specs */
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for (i = 0; i < 1000; i++)
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udelay(1000);
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/*
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* Configure PCI Local Access Windows
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*/
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out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
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out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
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out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI mem space - prefetch */
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out_be32(&pci_pot[0].potar,
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(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
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out_be32(&pci_pot[0].pobar,
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(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
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out_be32(&pci_pot[0].pocmr,
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POCMR_EN | POCMR_PRE | POCMR_CM_256M);
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/* PCI IO space */
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out_be32(&pci_pot[1].potar,
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(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
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out_be32(&pci_pot[1].pobar,
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(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
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out_be32(&pci_pot[1].pocmr,
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POCMR_EN | POCMR_IO | POCMR_CM_16M);
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/* PCI mmio - non-prefetch mem space */
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out_be32(&pci_pot[2].potar,
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(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
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out_be32(&pci_pot[2].pobar,
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(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
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out_be32(&pci_pot[2].pocmr,
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POCMR_EN | POCMR_CM_256M);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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out_be32(&pci_ctrl[0].pitar1, 0x0);
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out_be32(&pci_ctrl[0].pibar1, 0x0);
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out_be32(&pci_ctrl[0].piebar1, 0x0);
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out_be32(&pci_ctrl[0].piwar1,
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PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
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PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI_MEM_BASE,
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CONFIG_SYS_PCI_MEM_PHYS,
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CONFIG_SYS_PCI_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI_MMIO_BASE,
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CONFIG_SYS_PCI_MMIO_PHYS,
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CONFIG_SYS_PCI_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CONFIG_SYS_PCI_IO_BASE,
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CONFIG_SYS_PCI_IO_PHYS,
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CONFIG_SYS_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR + 0x8300),
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(CONFIG_SYS_IMMR + 0x8304));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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}
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int tmp[2];
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const char *path;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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path = fdt_getprop(blob, nodeoffset, "pci", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose.first_busno);
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tmp[1] = cpu_to_be32(pci_hose.last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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}
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}
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#endif /* CONFIG_OF_LIBFDT */
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