upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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101 lines
3.3 KiB
101 lines
3.3 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/* ide.c - ide support functions */
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#include <common.h>
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#ifdef CONFIG_CMD_IDE
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#include <ata.h>
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#include <ide.h>
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#include <pci.h>
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#define IT8212_PCI_CpuCONTROL 0x5e
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#define IT8212_PCI_PciModeCONTROL 0x50
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#define IT8212_PCI_IdeIoCONFIG 0x40
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#define IT8212_PCI_IdeBusSkewCONTROL 0x4c
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#define IT8212_PCI_IdeDrivingCURRENT 0x42
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extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
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extern struct pci_controller hose;
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int ide_preinit (void)
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{
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int status;
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pci_dev_t devbusfn;
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int l;
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status = 1;
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for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
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ide_bus_offset[l] = -ATA_STATUS;
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}
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devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
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if (devbusfn == -1)
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devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0);
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if (devbusfn != -1) {
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u32 ide_bus_offset32;
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status = 0;
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pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
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&ide_bus_offset32);
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ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
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ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
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ide_bus_offset[0] & 0xfffffffe,
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PCI_REGION_IO);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
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(u32 *) &ide_bus_offset[1]);
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ide_bus_offset[1] &= 0xfffffffe;
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ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
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ide_bus_offset[1] & 0xfffffffe,
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PCI_REGION_IO);
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}
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if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) {
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pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01);
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pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00);
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pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047);
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#ifdef CONFIG_IT8212_SECONDARY_ENABLE
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pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3);
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#else
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pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031);
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#endif
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pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204);
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/* __LS_COMMENT__ BUFFALO changed 2004.11.10 changed for EMI */
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pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
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/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
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/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
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/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
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/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
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pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
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}
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return (status);
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}
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void ide_set_reset (int flag) {
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return;
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}
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#endif /* CONFIG_CMD_IDE */
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