upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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107 lines
3.2 KiB
107 lines
3.2 KiB
/*
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* Configuation settings for the Hitachi Solution Engine 7750
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MS7750SE_H
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#define __MS7750SE_H
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#define CONFIG_SH 1
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#define CONFIG_SH4 1
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#define CONFIG_CPU_SH7750 1
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/* #define CONFIG_CPU_SH7751 1 */
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/* #define CONFIG_CPU_TYPE_R 1 */
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#define CONFIG_MS7750SE 1
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#define __LITTLE_ENDIAN__ 1
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/*
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* Command line configuration.
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*/
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/*#include <config_cmd_default.h>*/
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_ENV
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_CONS_SCIF1 1
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#define BOARD_LATE_INIT 1
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_BOOTARGS "console=ttySC0,38400"
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CFG_SDRAM_BASE (0x8C000000)
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#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
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#define CFG_LONGHELP
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#define CFG_PROMPT "=> "
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#define CFG_CBSIZE 256
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#define CFG_PBSIZE 256
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#define CFG_MAXARGS 16
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#define CFG_BARGSIZE 512
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/* List of legal baudrate settings for this board */
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#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
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#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
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/* NOR Flash */
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/* #define CFG_FLASH_BASE (0xA1000000)*/
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#define CFG_FLASH_BASE (0xA0000000)
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#define CFG_MAX_FLASH_BANKS (1) /* Max number of
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* Flash memory banks
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*/
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#define CFG_MAX_FLASH_SECT 142
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */
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#define CFG_MONITOR_LEN (128 * 1024)
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#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
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#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
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#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
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#define CFG_RX_ETH_BUFFER (8)
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#define CFG_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#undef CFG_FLASH_CFI_BROKEN_TABLE
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#undef CFG_FLASH_QUIET_TEST
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000
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#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_FLASH_ERASE_TOUT 120000
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#define CFG_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define TMU_CLK_DIVIDER 4
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#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
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#endif /* __MS7750SE_H */
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