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/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
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*
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* From:
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* (C) Copyright 2003
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* Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef USE_VGA_GRAPHICS
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/* Memory Map
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* 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
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* 0x74000000 .... 0x740FFFFF -> CS#6
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* 0x74100000 .... 0x741FFFFF -> CS#7
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* 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
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* 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
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* 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
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* 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
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* 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
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* 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
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* 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
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* 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
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*
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* 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
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* 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
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* 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
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* 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
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* 0xEED00000 .... 0xEED00003 -> PCI-Bus
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* 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
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* 0xEF40003F .... 0xEF5FFFFF -> reserved
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* 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
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* 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
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* 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
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* 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
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* 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
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* 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
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*/
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#define CONFIG_SC3 1
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#define CONFIG_4xx 1
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#define CONFIG_405GP 1
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/*
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* Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
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* If undefined, IDE access uses a seperat emulation with higher access speed.
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* Consider to inform your Linux IDE driver about the different addresses!
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* IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
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*/
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#define IDE_USES_ISA_EMULATION
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_SERIAL_MULTI
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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/*
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* define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
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* Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
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*/
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#if CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_POWER_DOWN
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#endif
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/*
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* define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
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*/
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#define CONFIG_SYS_CLK_FREQ 33333333
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/*
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* define CONFIG_BAUDRATE to the baudrate value you want to use as default
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
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"rootfstype=jffs2\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addcons=setenv bootargs ${bootargs} " \
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"console=ttyS0,${baudrate}\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr}\0" \
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"flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/sc3/uImage\0" \
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"u-boot=/tftpboot/sc3/u-boot.bin\0" \
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"setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \
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"kernel_addr=FFE08000\0" \
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""
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
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#if 1 /* feel free to disable for development */
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#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
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#define CONFIG_AUTOBOOT_PROMPT \
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"\nSC3 - booting... stop with ENTER\n"
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#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
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#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
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#endif
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/*
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* define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
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* the CONFIG_BOOTDELAY delay to boot your machine
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*/
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#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
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/*
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* define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
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* set different values at the u-boot prompt
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*/
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#ifdef USE_VGA_GRAPHICS
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#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
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#else
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
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#endif
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/*
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* Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
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* This reserves memory bank #4 for this purpose
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*/
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#undef CONFIG_ISP1161_PRESENT
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#undef CONFIG_LOADS_ECHO /* no echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI
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/* #define CONFIG_EEPRO100_SROM_WRITE */
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/* #define CONFIG_SHOW_MAC */
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#define CONFIG_EEPRO100
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#define CONFIG_MII 1 /* add 405GP MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_AUTOSCRIPT
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_ELF
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP 1 /* undef to save memory */
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#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*
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* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*
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* Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
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* (see 405GP datasheet for descritpion)
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*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CFG_BASE_BAUD 921600 /* internal clock */
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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#define CFG_LOAD_ADDR 0x1000000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* IIC stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define I2C_INIT
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#define I2C_ACTIVE 0
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#define I2C_TRISTATE 0
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#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
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#define CFG_I2C_SLAVE 0x7F /* mask valid bits */
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#define CONFIG_RTC_DS1337
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#define CFG_I2C_RTC_ADDR 0x68
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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/* If you want to see, whats connected to your PCI bus */
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/* #define CONFIG_PCI_SCAN_SHOW */
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#if !defined(CONFIG_CMD_IDE)
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#else
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#define CONFIG_START_IDE 1 /* check, if use IDE */
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CONFIG_ATAPI
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#define CONFIG_DOS_PARTITION
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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#ifndef IDE_USES_ISA_EMULATION
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/* New and faster access */
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#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
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/* How many IDE busses are available */
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#define CFG_IDE_MAXBUS 1
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/* What IDE ports are available */
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#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
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#undef CFG_ATA_IDE1_OFFSET /* second not available */
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/* access to the data port is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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/* access to the registers is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
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/* access to the alternate register is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
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#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
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#else /* IDE_USES_ISA_EMULATION */
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#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
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/* How many IDE busses are available */
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#define CFG_IDE_MAXBUS 1
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/* What IDE ports are available */
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#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
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#undef CFG_ATA_IDE1_OFFSET /* second not available */
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/* access to the data port is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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/* access to the registers is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
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/* access to the alternate register is calculated:
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CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
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#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
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#endif /* IDE_USES_ISA_EMULATION */
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#endif
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/*
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#define CFG_KEY_REG_BASE_ADDR 0xF0100000
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#define CFG_IR_REG_BASE_ADDR 0xF0200000
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#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
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*/
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*
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* CFG_FLASH_BASE -> start address of internal flash
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* CFG_MONITOR_BASE -> start of u-boot
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*/
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#ifndef __ASSEMBLER__
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extern unsigned long offsetOfBigFlash;
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extern unsigned long offsetOfEnvironment;
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#endif
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFE00000
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#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
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#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
|
|
|
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
|
|
|
|
|
|
/*
|
|
|
* For booting Linux, the board info and command line data
|
|
|
* have to be in the first 8 MiB of memory, since this is
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
*/
|
|
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
|
/*-----------------------------------------------------------------------
|
|
|
* FLASH organization ## FIXME: lookup in datasheet
|
|
|
*/
|
|
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
|
|
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
|
|
|
|
|
#define CFG_FLASH_CFI /* flash is CFI compat. */
|
|
|
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
|
|
|
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
|
|
|
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
|
|
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
|
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
|
|
#define CFG_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */
|
|
|
|
|
|
#define CFG_ENV_IS_IN_FLASH 1
|
|
|
#if CFG_ENV_IS_IN_FLASH
|
|
|
#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
|
|
|
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
|
|
#define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
|
|
|
|
|
|
/* Address and size of Redundant Environment Sector */
|
|
|
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
|
|
|
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
|
|
|
|
|
#endif
|
|
|
/* let us changing anything in our environment */
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
|
|
/*
|
|
|
* NAND-FLASH stuff
|
|
|
*/
|
|
|
#define CFG_MAX_NAND_DEVICE 1
|
|
|
#define NAND_MAX_CHIPS 1
|
|
|
#define CFG_NAND_BASE 0x77D00000
|
|
|
|
|
|
|
|
|
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
|
|
|
|
|
|
/* No command line, one static partition */
|
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
|
#define CONFIG_JFFS2_DEV "nand0"
|
|
|
#define CONFIG_JFFS2_PART_SIZE 0x01000000
|
|
|
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
|
|
|
|
|
/*
|
|
|
* Init Memory Controller:
|
|
|
*
|
|
|
*/
|
|
|
|
|
|
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
|
|
|
#define FLASH_BASE1_PRELIM 0
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
* Some informations about the internal SRAM (OCM=On Chip Memory)
|
|
|
*
|
|
|
* CFG_OCM_DATA_ADDR -> location
|
|
|
* CFG_OCM_DATA_SIZE -> size
|
|
|
*/
|
|
|
|
|
|
#define CFG_TEMP_STACK_OCM 1
|
|
|
#define CFG_OCM_DATA_ADDR 0xF8000000
|
|
|
#define CFG_OCM_DATA_SIZE 0x1000
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
* Definitions for initial stack pointer and data area (in DPRAM):
|
|
|
* - we are using the internal 4k SRAM, so we don't need data cache mapping
|
|
|
* - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
|
|
|
* - Stackpointer will be located to
|
|
|
* (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
|
|
|
* in cpu/ppc4xx/start.S
|
|
|
*/
|
|
|
|
|
|
#undef CFG_INIT_DCACHE_CS
|
|
|
/* Where the internal SRAM starts */
|
|
|
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
|
|
|
/* Where the internal SRAM ends (only offset) */
|
|
|
#define CFG_INIT_RAM_END 0x0F00
|
|
|
|
|
|
/*
|
|
|
|
|
|
CFG_INIT_RAM_ADDR ------> ------------ lower address
|
|
|
| |
|
|
|
| ^ |
|
|
|
| | |
|
|
|
| | Stack |
|
|
|
CFG_GBL_DATA_OFFSET ----> ------------
|
|
|
| |
|
|
|
| 64 Bytes |
|
|
|
| |
|
|
|
CFG_INIT_RAM_END ------> ------------ higher address
|
|
|
(offset only)
|
|
|
|
|
|
*/
|
|
|
/* size in bytes reserved for initial data */
|
|
|
#define CFG_GBL_DATA_SIZE 64
|
|
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
|
|
/* Initial value of the stack pointern in internal SRAM */
|
|
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
|
|
|
|
|
/*
|
|
|
* Internal Definitions
|
|
|
*
|
|
|
* Boot Flags
|
|
|
*/
|
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
|
|
/* ################################################################################### */
|
|
|
/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
|
|
|
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
|
|
|
|
|
|
/* This chip select accesses the boot device */
|
|
|
/* It depends on boot select switch if this device is 16 or 8 bit */
|
|
|
|
|
|
#undef CFG_EBC_PB0AP
|
|
|
#undef CFG_EBC_PB0CR
|
|
|
|
|
|
#undef CFG_EBC_PB1AP
|
|
|
#undef CFG_EBC_PB1CR
|
|
|
|
|
|
#undef CFG_EBC_PB2AP
|
|
|
#undef CFG_EBC_PB2CR
|
|
|
|
|
|
#undef CFG_EBC_PB3AP
|
|
|
#undef CFG_EBC_PB3CR
|
|
|
|
|
|
#undef CFG_EBC_PB4AP
|
|
|
#undef CFG_EBC_PB4CR
|
|
|
|
|
|
#undef CFG_EBC_PB5AP
|
|
|
#undef CFG_EBC_PB5CR
|
|
|
|
|
|
#undef CFG_EBC_PB6AP
|
|
|
#undef CFG_EBC_PB6CR
|
|
|
|
|
|
#undef CFG_EBC_PB7AP
|
|
|
#undef CFG_EBC_PB7CR
|
|
|
|
|
|
#define CFG_EBC_CFG 0xb84ef000
|
|
|
|
|
|
#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
|
|
|
#undef CONFIG_SPD_EEPROM
|
|
|
|
|
|
/*
|
|
|
* Define this to get more information about system configuration
|
|
|
*/
|
|
|
/* #define SC3_DEBUGOUT */
|
|
|
#undef SC3_DEBUGOUT
|
|
|
|
|
|
/***********************************************************************
|
|
|
* External peripheral base address
|
|
|
***********************************************************************/
|
|
|
|
|
|
#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
|
|
|
/*
|
|
|
Die Grafik-Treiber greifen <EFBFBD>ber die Adresse in diesem Macro auf den Chip zu.
|
|
|
Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
|
|
|
das gleiche Mapping durchf<EFBFBD>hren kann, wie der SC520 (also Aufteilen von IO-Zugriffen
|
|
|
auf ISA- und PCI-Zyklen)
|
|
|
*/
|
|
|
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
|
|
|
/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
|
|
|
|
|
|
/************************************************************
|
|
|
* Video support
|
|
|
************************************************************/
|
|
|
|
|
|
#ifdef USE_VGA_GRAPHICS
|
|
|
#define CONFIG_VIDEO /* To enable video controller support */
|
|
|
#define CONFIG_VIDEO_CT69000
|
|
|
#define CONFIG_CFB_CONSOLE
|
|
|
/* #define CONFIG_VIDEO_LOGO */
|
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
|
#define CONFIG_VIDEO_SW_CURSOR
|
|
|
/* #define CONFIG_VIDEO_HW_CURSOR */
|
|
|
#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
|
|
|
|
|
|
#define VIDEO_HW_RECTFILL
|
|
|
#define VIDEO_HW_BITBLT
|
|
|
|
|
|
#endif
|
|
|
|
|
|
/************************************************************
|
|
|
* Ident
|
|
|
************************************************************/
|
|
|
#define CONFIG_SC3_VERSION "r1.4"
|
|
|
|
|
|
#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
|
|
|
|
|
|
#endif /* __CONFIG_H */
|
|
|
|
