upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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133 lines
3.6 KiB
133 lines
3.6 KiB
/*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <asm/mach-types.h>
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#include "evm.h"
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: misc_init_r
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* Description: Init ethernet (done here so udelay works)
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*/
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int misc_init_r(void)
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{
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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#if defined(CONFIG_CMD_NET)
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setup_net_chip();
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#endif
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_EVM();
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}
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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/* Configure GPMC registers */
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writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
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writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
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writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
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writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
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writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
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writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
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writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
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writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
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&ctrl_base->gpmc_nadv_ale);
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/* Make GPIO 64 as output pin */
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writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
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/* Now send a pulse on the GPIO pin */
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writel(GPIO0, &gpio3_base->setdataout);
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udelay(1);
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writel(GPIO0, &gpio3_base->cleardataout);
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udelay(1);
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writel(GPIO0, &gpio3_base->setdataout);
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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