upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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188 lines
7.6 KiB
188 lines
7.6 KiB
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Define this to make U-Boot skip low level initialization when loaded
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* by initial bootloader. Not required by NAND U-Boot version but IS
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* required for a NOR version used to burn the real NOR U-Boot into
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* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
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* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
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* NOR U-Boot is loaded directly from Flash so it must perform all the
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* low level initialization itself. NAND version is loaded by an initial
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* bootloader (UBL in TI-ese) that performs such an initialization so it's
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* skipped in NAND version. The third DaVinci boot mode loads a bootloader
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* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
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* performing low level init prior to loading. All that means we can NOT use
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* NAND version to put U-Boot into NOR because it doesn't have NOR support and
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* we can NOT use NOR version because it performs low level initialization
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* effectively destroying itself in DDR memory. That's why a separate NOR
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* version with this define is needed. It is loaded via UART, then one uses
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* it to somehow download a proper NOR version built WITHOUT this define to
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* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
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* NOR support into the initial bootloader so it won't be needed but DaVinci
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* static RAM might be too small for this (I have something like 2Kbytes left
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* as of now, without NOR support) so this might've not happened...
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*
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#define CONFIG_NOR_UART_BOOT
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*/
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/*=======*/
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/* Board */
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/*=======*/
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#define SONATA_BOARD
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#define CONFIG_SYS_NAND_SMALLPAGE
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#define CONFIG_SYS_USE_NOR
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#define MACH_TYPE_SONATA 1254
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#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
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/*===================*/
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/* SoC Configuration */
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/*===================*/
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#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CONFIG_SOC_DM644X
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/*====================================================*/
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/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
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/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
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/*====================================================*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/*=============*/
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/* Memory Info */
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/*=============*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
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#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
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#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
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#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
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/*====================*/
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/* Serial Driver info */
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/*====================*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
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#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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/*===================*/
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/* I2C Configuration */
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/*===================*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_DAVINCI
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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/*==================================*/
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/* Network & Ethernet Configuration */
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/*==================================*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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/*=====================*/
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/* Flash & Environment */
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/*=====================*/
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#ifdef CONFIG_SYS_USE_NAND
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_CS 2
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
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#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
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#define CONFIG_SYS_NAND_BASE 0x02000000
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#define CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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#elif defined(CONFIG_SYS_USE_NOR)
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#ifdef CONFIG_NOR_UART_BOOT
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
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#else
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#undef CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_SYS_NO_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
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#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
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#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
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#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
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#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
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#endif
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/*==============================*/
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/* U-Boot general configuration */
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/*==============================*/
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#define CONFIG_MISC_INIT_R
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#undef CONFIG_BOOTDELAY
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/*===================*/
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/* Linux Information */
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/*===================*/
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#define LINUX_BOOT_PARAM_ADDR 0x80000100
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
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#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
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/*=================*/
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/* U-Boot commands */
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/*=================*/
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_EEPROM
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#ifdef CONFIG_SYS_USE_NAND
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#define CONFIG_CMD_NAND
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#elif defined(CONFIG_SYS_USE_NOR)
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#define CONFIG_CMD_JFFS2
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#else
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#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
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#endif
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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