upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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222 lines
5.4 KiB
222 lines
5.4 KiB
/*
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* Palm Tungsten|C configuration file
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*
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* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/pxa-regs.h>
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
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#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_BOOTCOMMAND \
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"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
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"source 0xa0000000; " \
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"else " \
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"bootm 0x80000; " \
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"fi; "
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#define CONFIG_BOOTARGS \
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"console=tty0 console=ttyS0,115200"
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_LZMA /* LZMA compression support */
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/*
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* Serial Console Configuration
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* STUART - the lower serial port on Colibri board
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_BAUDRATE 115200
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/*
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* Bootloader Components Configuration
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*/
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_MMC
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#define CONFIG_LCD
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#define CONFIG_PXA_LCD
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/*
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* MMC Card Configuration
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* LCD
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*/
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#ifdef CONFIG_LCD
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#define CONFIG_ACX517AKN
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CMD_BMP
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
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#endif
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/*
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* KGDB
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*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
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#endif
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/*
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* HUSH Shell Configuration
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_LONGHELP
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ "
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
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/*
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* NOR FLASH
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*/
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#ifdef CONFIG_CMD_FLASH
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 64
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
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#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#else
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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#define CONFIG_SYS_MONITOR_BASE 0x0
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_ENV_SIZE 0x4000
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#define CONFIG_ENV_ADDR 0x40000
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GAFR0_L_VAL 0x00011004
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
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#define CONFIG_SYS_GAFR1_L_VAL 0x60888050
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
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#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
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#define CONFIG_SYS_GPCR0_VAL 0x0
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#define CONFIG_SYS_GPCR1_VAL 0x0
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#define CONFIG_SYS_GPCR2_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xcfff8140
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#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
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#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
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#define CONFIG_SYS_GPSR0_VAL 0x00010f8f
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#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
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#define CONFIG_SYS_GPSR2_VAL 0x03fe0800
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#define CONFIG_SYS_PSSR_VAL PSSR_RDH
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/* Clock setup:
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* CKEN[1] - PWM1 ; CKEN[6] - FFUART
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* CKEN[12] - MMC ; CKEN[16] - LCD
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*/
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#define CONFIG_SYS_CKEN 0x00011042
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#define CONFIG_SYS_CCCR 0x00000161
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x800092c2
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#define CONFIG_SYS_MSC1_VAL 0x80008000
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#define CONFIG_SYS_MSC2_VAL 0x80008000
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#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
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#define CONFIG_SYS_MDREFR_VAL 0x00118018
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#define CONFIG_SYS_MDMRS_VAL 0x00220032
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#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000000
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#define CONFIG_SYS_MCMEM0_VAL 0x00010504
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#define CONFIG_SYS_MCMEM1_VAL 0x00010504
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#define CONFIG_SYS_MCATT0_VAL 0x00010504
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#define CONFIG_SYS_MCATT1_VAL 0x00010504
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#define CONFIG_SYS_MCIO0_VAL 0x00010e04
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#define CONFIG_SYS_MCIO1_VAL 0x00010e04
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#endif /* __CONFIG_H */
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