upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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312 lines
8.4 KiB
312 lines
8.4 KiB
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
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#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
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#define CONFIG_SYS_GENERIC_BOARD
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/* Virtual target or real hardware */
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#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_THUMB_BUILD
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/*
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* High level configuration
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_CLOCKS
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#define CONFIG_FIT
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#define CONFIG_OF_LIBFDT
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#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x0
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#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TEXT_BASE 0x08000040
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#else
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#define CONFIG_SYS_TEXT_BASE 0x01000040
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#endif
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/*
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* U-Boot general configurations
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print buffer size */
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#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
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#define CONFIG_AUTO_COMPLETE /* Command auto complete */
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#define CONFIG_CMDLINE_EDITING /* Command history etc */
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#define CONFIG_SYS_HUSH_PARSER
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/*
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* Cache
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*/
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#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_L2_PL310
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#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
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/*
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* EPCS/EPCQx1 Serial Flash Controller
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*/
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#ifdef CONFIG_ALTERA_SPI
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_BAR
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/*
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* The base address is configurable in QSys, each board must specify the
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* base address based on it's particular FPGA configuration. Please note
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* that the address here is incremented by 0x400 from the Base address
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* selected in QSys, since the SPI registers are at offset +0x400.
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* #define CONFIG_SYS_SPI_BASE 0xff240400
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*/
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#endif
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/*
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* Ethernet on SoC (EMAC)
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*/
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#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define CONFIG_DW_ALTDESCRIPTOR
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#define CONFIG_MII
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#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_GIGE
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#endif
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/*
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* FPGA Driver
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*/
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#ifdef CONFIG_CMD_FPGA
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#define CONFIG_FPGA
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_SOCFPGA
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#define CONFIG_FPGA_COUNT 1
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#endif
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/*
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* L4 OSC1 Timer 0
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*/
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/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
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#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_TIMER_RATE 2400000
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#else
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#define CONFIG_SYS_TIMER_RATE 25000000
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#endif
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/*
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* L4 Watchdog
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*/
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#ifdef CONFIG_HW_WATCHDOG
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#define CONFIG_DESIGNWARE_WATCHDOG
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#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
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#define CONFIG_DW_WDT_CLOCK_KHZ 25000
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#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
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#endif
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/*
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* MMC Driver
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DWMMC
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#define CONFIG_SOCFPGA_DWMMC
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#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
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#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
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#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
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/* FIXME */
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/* using smaller max blk cnt to avoid flooding the limited stack we have */
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
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#endif
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/*
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* I2C support
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_DW
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#define CONFIG_SYS_I2C_BUS_MAX 4
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#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
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#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
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#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
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#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
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/* Using standard mode which the speed up to 100Kb/s */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SPEED1 100000
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#define CONFIG_SYS_I2C_SPEED2 100000
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#define CONFIG_SYS_I2C_SPEED3 100000
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/* Address of device when used as slave */
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#define CONFIG_SYS_I2C_SLAVE 0x02
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#define CONFIG_SYS_I2C_SLAVE1 0x02
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#define CONFIG_SYS_I2C_SLAVE2 0x02
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#define CONFIG_SYS_I2C_SLAVE3 0x02
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#ifndef __ASSEMBLY__
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/* Clock supplied to I2C controller in unit of MHz */
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unsigned int cm_get_l4_sp_clk_hz(void);
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#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
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#endif
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#define CONFIG_CMD_I2C
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/*
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* QSPI support
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*/
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#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
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#define CONFIG_CADENCE_QSPI
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/* Enable multiple SPI NOR flash manufacturers */
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#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
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#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
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#define CONFIG_SPI_FLASH_MTD
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/* QSPI reference clock */
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#ifndef __ASSEMBLY__
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unsigned int cm_get_qspi_controller_clk_hz(void);
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#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
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#endif
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_CMD_SF
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#endif
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#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
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#define CONFIG_DESIGNWARE_SPI
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#define CONFIG_CMD_SPI
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#endif
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/*
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* Serial Driver
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_NS16550_CLK 1000000
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#else
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#define CONFIG_SYS_NS16550_CLK 100000000
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#endif
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/*
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* USB
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*/
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_DWC2
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#define CONFIG_USB_STORAGE
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/*
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* NOTE: User must define either of the following to select which
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* of the two USB controllers available on SoCFPGA to use.
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* The DWC2 driver doesn't support multiple USB controllers.
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* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
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* #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
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*/
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#endif
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/*
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* USB Gadget (DFU, UMS)
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*/
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#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_S3C_UDC_OTG
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#define CONFIG_USB_GADGET_DUALSPEED
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#define CONFIG_USB_GADGET_VBUS_DRAW 2
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/* USB Composite download gadget - g_dnl */
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#define CONFIG_USB_GADGET_DOWNLOAD
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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#define CONFIG_USB_FUNCTION_DFU
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#define CONFIG_DFU_MMC
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#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
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#define DFU_DEFAULT_POLL_TIMEOUT 300
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/* USB IDs */
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#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
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#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
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#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
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#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
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#ifndef CONFIG_G_DNL_MANUFACTURER
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#define CONFIG_G_DNL_MANUFACTURER "Altera"
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#endif
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#endif
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/*
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* U-Boot environment
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*/
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 4096
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/*
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* SPL
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*
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* SRAM Memory layout:
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*
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* 0xFFFF_0000 ...... Start of SRAM
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* 0xFFFF_xxxx ...... Top of stack (grows down)
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* 0xFFFF_yyyy ...... Malloc area
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* 0xFFFF_zzzz ...... Global Data
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* 0xFFFF_FF00 ...... End of SRAM
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*/
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_RAM_DEVICE
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#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
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#define CONFIG_SPL_MAX_SIZE (64 * 1024)
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#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
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#define CONFIG_CRC32_VERIFY
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/* Linker script for SPL */
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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/*
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* Stack setup
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*/
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#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_PARTITIONS
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#endif
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#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
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