upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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139 lines
4.9 KiB
139 lines
4.9 KiB
/*
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* (C) Copyright 2002
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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long int fixed_sdram( void );
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int board_pre_init (void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr( ebccfga, xbcfg );
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reg = mfdcr( ebccfgd );
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mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
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mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
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mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
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/* test-only: other regs still missing... */
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr( uic0sr, 0xffffffff ); /* clear all */
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mtdcr( uic0er, 0x00000000 ); /* disable all */
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mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
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mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
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mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
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mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
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mtdcr( uic0sr, 0xffffffff ); /* clear all */
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mtdcr( uic1sr, 0xffffffff ); /* clear all */
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mtdcr( uic1er, 0x00000000 ); /* disable all */
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mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
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mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
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mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
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mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
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mtdcr( uic1sr, 0xffffffff ); /* clear all */
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return 0;
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}
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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printf("Board: esd CPCI-440\n");
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printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
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printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
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printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
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printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
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printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
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return (0);
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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dram_size = fixed_sdram();
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return dram_size;
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}
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 64 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram( void )
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
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mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
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mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
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mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
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mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
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mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
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udelay( 400 ); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
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for(;;)
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{
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mfsdram( mem_mcsts, reg );
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if( reg & 0x80000000 )
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break;
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}
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return( 64 * 1024 * 1024 ); /* 64 MB */
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}
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