upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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523 lines
21 KiB
523 lines
21 KiB
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* kilauea.h - configuration for AMCC Kilauea (405EX)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_KILAUEA 1 /* Board is Kilauea */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EX 1 /* Specifc 405EX support*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_EMAC_COUNT
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFC000000
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#define CFG_NAND_ADDR 0xF8000000
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#define CFG_FPGA_BASE 0xF0000000
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#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
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#define CFG_MONITOR_BASE (TEXT_BASE)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/* reserve some memory for POST and BOOT limit info */
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#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
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/* extra data in init-ram */
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
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#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
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#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
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#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
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#define CFG_NAND_ECCSIZE 256
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#define CFG_NAND_ECCBYTES 3
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#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CFG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
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#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* Standard DTT sensor configuration */
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#define CONFIG_DTT_DS1775 1
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#define CONFIG_DTT_SENSORS { 0 }
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#define CFG_I2C_DTT_ADDR 0x48
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/* RTC configuration */
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#define CONFIG_RTC_DS1338 1
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#define CFG_I2C_RTC_ADDR 0x68
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/*-----------------------------------------------------------------------
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* Ethernet
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*----------------------------------------------------------------------*/
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#define CONFIG_M88E1111_PHY 1
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 2
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"logversion=2\0" \
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"netdev=eth0\0" \
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"hostname=kilauea\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addtty;" \
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"bootm 200000\0" \
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"net_nfs_fdt=tftp 200000 ${bootfile};" \
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"tftp ${fdt_addr} ${fdt_file};" \
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"run nfsargs addip addtty;" \
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"bootm 200000 - ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=kilauea/uImage\0" \
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"fdt_file=kilauea/kilauea.dtb\0" \
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"fdt_addr=400000\0" \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc200000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 200000 kilauea/u-boot.bin\0" \
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"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
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"cp.b ${fileaddr} fffa0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"nload=tftp 200000 kilauea/u-boot-nand.bin\0" \
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"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
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"setenv filesize;saveenv\0" \
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"nupd=run nload nupdate\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_LOG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SNTP
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ETHER | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_UART)
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/* Define here the base-addresses of the UARTs to test in POST */
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#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
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#define CONFIG_LOGBUFFER
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#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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/*-----------------------------------------------------------------------
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* PCI stuff
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*----------------------------------------------------------------------*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/*-----------------------------------------------------------------------
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* PCIe stuff
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*----------------------------------------------------------------------*/
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#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
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#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
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#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
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#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
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#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
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#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
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#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
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#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
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#define CFG_PCIE0_UTLBASE 0xef502000
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#define CFG_PCIE1_UTLBASE 0xef503000
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/* base address of inbound PCIe window */
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#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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/* booting from NAND, so NAND chips select has to be on CS 0 */
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#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 1 (NOR-FLASH) initialization */
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#define CFG_EBC_PB1AP 0x05806500
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#define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
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/* Memory Bank 0 (NAND-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x018003c0
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#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000)
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#else
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#define CFG_NAND_CS 1 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x05806500
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#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
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/* Memory Bank 1 (NAND-FLASH) initialization */
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#define CFG_EBC_PB1AP 0x018003c0
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#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000)
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#endif
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/* Memory Bank 2 (FPGA) initialization */
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#define CFG_EBC_PB2AP 0x9400C800
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
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{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
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} \
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}
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*-----------------------------------------------------------------------
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* Some Kilauea stuff..., mainly fpga registers
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*/
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#define CFG_FPGA_REG_BASE CFG_FPGA_BASE
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#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11))
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/* interrupt */
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#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000
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#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000
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#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000
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#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000
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#define CFG_FPGA_PHY0_INT 0x08000000
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#define CFG_FPGA_PHY1_INT 0x04000000
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#define CFG_FPGA_SLIC0_INT 0x02000000
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#define CFG_FPGA_SLIC1_INT 0x01000000
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/* DPRAM setting */
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/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
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#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
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#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
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#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000
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#define CFG_FPGA_DPRAM_RST 0x00040000
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#define CFG_FPGA_UART0_FO 0x00020000
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#define CFG_FPGA_UART1_FO 0x00010000
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/* loopback */
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#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000
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#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000
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#define CFG_FPGA_SLIC0_ENABLE 0x00002000
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#define CFG_FPGA_SLIC1_ENABLE 0x00001000
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#define CFG_FPGA_SLIC0_CS 0x00000800
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#define CFG_FPGA_SLIC1_CS 0x00000400
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#define CFG_FPGA_USER_LED0 0x00000200
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#define CFG_FPGA_USER_LED1 0x00000100
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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