upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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138 lines
3.8 KiB
138 lines
3.8 KiB
/*
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* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_NIOS_IO_H_
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#define __ASM_NIOS_IO_H_
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#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __raw_readb(a) (*(volatile unsigned char *)(a))
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#define __raw_readw(a) (*(volatile unsigned short *)(a))
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#define __raw_readl(a) (*(volatile unsigned int *)(a))
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#define readb(addr)\
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({unsigned char val;\
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asm volatile( " pfxio 0 \n"\
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" ld %0, [%1] \n"\
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" ext8d %0, %1 \n"\
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:"=r"(val) : "r" (addr)); val;})
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#define readw(addr)\
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({unsigned short val;\
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asm volatile( " pfxio 0 \n"\
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" ld %0, [%1] \n"\
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" ext16d %0, %1 \n"\
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:"=r"(val) : "r" (addr)); val;})
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#define readl(addr)\
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({unsigned long val;\
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asm volatile( " pfxio 0 \n"\
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" ld %0, [%1] \n"\
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:"=r"(val) : "r" (addr)); val;})
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#define writeb(addr,val)\
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asm volatile ( " fill8 %%r0, %1 \n"\
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" st8d [%0], %%r0 \n"\
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: : "r" (addr), "r" (val) : "r0")
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#define writew(addr,val)\
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asm volatile ( " fill16 %%r0, %1 \n"\
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" st16d [%0], %%r0 \n"\
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: : "r" (addr), "r" (val) : "r0")
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#define writel(addr,val)\
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asm volatile ( " st [%0], %1 \n"\
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: : "r" (addr), "r" (val))
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#define inb(addr) readb(addr)
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#define inw(addr) readw(addr)
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#define inl(addr) readl(addr)
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#define outb(val,addr) writeb(addr,val)
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#define outw(val,addr) writew(addr,val)
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#define outl(val,addr) writel(addr,val)
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static inline void insb (unsigned long port, void *dst, unsigned long count)
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{
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unsigned char *p = dst;
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while (count--) *p++ = inb (port);
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}
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static inline void insw (unsigned long port, void *dst, unsigned long count)
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{
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unsigned short *p = dst;
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while (count--) *p++ = inw (port);
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}
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static inline void insl (unsigned long port, void *dst, unsigned long count)
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{
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unsigned long *p = dst;
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while (count--) *p++ = inl (port);
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}
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static inline void outsb (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned char *p = src;
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while (count--) outb (*p++, port);
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}
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static inline void outsw (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned short *p = src;
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while (count--) outw (*p++, port);
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}
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static inline void outsl (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned long *p = src;
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while (count--) outl (*p++, port);
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}
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static inline void sync(void)
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{
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}
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/*
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* Given a physical address and a length, return a virtual address
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* that can be used to access the memory range with the caching
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* properties specified by "flags".
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*/
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typedef unsigned long phys_addr_t;
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#define MAP_NOCACHE (0)
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#define MAP_WRCOMBINE (0)
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#define MAP_WRBACK (0)
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#define MAP_WRTHROUGH (0)
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static inline void *
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map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
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{
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return (void *)paddr;
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}
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/*
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* Take down a mapping set up by map_physmem().
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*/
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static inline void unmap_physmem(void *vaddr, unsigned long flags)
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{
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}
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#endif /* __ASM_NIOS_IO_H_ */
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