upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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387 lines
9.3 KiB
387 lines
9.3 KiB
/*
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* MCF5441x Internal Memory Map
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*
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* Copyright 2010-2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5441X__
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#define __IMMAP_5441X__
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/* Module Base Addresses */
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#define MMAP_XBS 0xFC004000
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#define MMAP_FBCS 0xFC008000
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#define MMAP_CAN0 0xFC020000
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#define MMAP_CAN1 0xFC024000
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#define MMAP_I2C1 0xFC038000
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#define MMAP_DSPI1 0xFC03C000
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#define MMAP_SCM 0xFC040000
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#define MMAP_PM 0xFC04002C
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#define MMAP_EDMA 0xFC044000
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#define MMAP_INTC0 0xFC048000
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#define MMAP_INTC1 0xFC04C000
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#define MMAP_INTC2 0xFC050000
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#define MMAP_IACK 0xFC054000
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#define MMAP_I2C0 0xFC058000
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#define MMAP_DSPI0 0xFC05C000
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#define MMAP_UART0 0xFC060000
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#define MMAP_UART1 0xFC064000
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#define MMAP_UART2 0xFC068000
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#define MMAP_UART3 0xFC06C000
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#define MMAP_DTMR0 0xFC070000
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#define MMAP_DTMR1 0xFC074000
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#define MMAP_DTMR2 0xFC078000
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#define MMAP_DTMR3 0xFC07C000
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#define MMAP_PIT0 0xFC080000
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#define MMAP_PIT1 0xFC084000
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#define MMAP_PIT2 0xFC088000
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#define MMAP_PIT3 0xFC08C000
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#define MMAP_EPORT0 0xFC090000
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#define MMAP_ADC 0xFC094000
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#define MMAP_DAC0 0xFC098000
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#define MMAP_DAC1 0xFC09C000
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#define MMAP_RRTC 0xFC0A8000
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#define MMAP_SIM 0xFC0AC000
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#define MMAP_USBOTG 0xFC0B0000
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#define MMAP_USBEHCI 0xFC0B4000
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#define MMAP_SDRAM 0xFC0B8000
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#define MMAP_SSI0 0xFC0BC000
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#define MMAP_PLL 0xFC0C0000
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#define MMAP_RNG 0xFC0C4000
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#define MMAP_SSI1 0xFC0C8000
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#define MMAP_ESDHC 0xFC0CC000
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#define MMAP_FEC0 0xFC0D4000
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#define MMAP_FEC1 0xFC0D8000
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#define MMAP_L2_SW0 0xFC0DC000
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#define MMAP_L2_SW1 0xFC0E0000
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#define MMAP_NFC_RAM 0xFC0FC000
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#define MMAP_NFC 0xFC0FF000
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#define MMAP_1WIRE 0xEC008000
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#define MMAP_I2C2 0xEC010000
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#define MMAP_I2C3 0xEC014000
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#define MMAP_I2C4 0xEC018000
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#define MMAP_I2C5 0xEC01C000
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#define MMAP_DSPI2 0xEC038000
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#define MMAP_DSPI3 0xEC03C000
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#define MMAP_UART4 0xEC060000
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#define MMAP_UART5 0xEC064000
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#define MMAP_UART6 0xEC068000
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#define MMAP_UART7 0xEC06C000
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#define MMAP_UART8 0xEC070000
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#define MMAP_UART9 0xEC074000
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#define MMAP_RCM 0xEC090000
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#define MMAP_CCM 0xEC090000
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#define MMAP_GPIO 0xEC094000
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#include <asm/coldfire/crossbar.h>
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#include <asm/coldfire/dspi.h>
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#include <asm/coldfire/edma.h>
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/flexcan.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/ssi.h>
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/* Serial Boot Facility (SBF) */
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typedef struct sbf {
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u8 resv0[0x18];
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u16 sbfsr; /* Serial Boot Facility Status */
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u8 resv1[0x6];
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u16 sbfcr; /* Serial Boot Facility Control */
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} sbf_t;
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/* Reset Controller Module (RCM) */
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typedef struct rcm {
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u8 rcr;
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u8 rsr;
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} rcm_t;
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/* Chip Configuration Module (CCM) */
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typedef struct ccm {
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u8 ccm_resv0[0x4]; /* 0x00 */
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u16 ccr; /* 0x04 Chip Configuration */
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u8 resv1[0x2]; /* 0x06 */
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u16 rcon; /* 0x08 Reset Configuration */
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u16 cir; /* 0x0A Chip Identification */
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u8 resv2[0x2]; /* 0x0C */
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u16 misccr; /* 0x0E Miscellaneous Control */
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u16 cdrh; /* 0x10 Clock Divider */
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u16 cdrl; /* 0x12 Clock Divider */
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u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
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u16 uhcsr; /* 0x16 */
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u16 misccr3; /* 0x18 */
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u16 misccr2; /* 0x1A */
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u16 adctsr; /* 0x1C */
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u16 dactsr; /* 0x1E */
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u16 sbfsr; /* 0x20 */
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u16 sbfcr; /* 0x22 */
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u32 fnacr; /* 0x24 */
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} ccm_t;
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/* General Purpose I/O Module (GPIO) */
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typedef struct gpio {
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u8 podr_a; /* 0x00 */
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u8 podr_b; /* 0x01 */
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u8 podr_c; /* 0x02 */
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u8 podr_d; /* 0x03 */
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u8 podr_e; /* 0x04 */
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u8 podr_f; /* 0x05 */
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u8 podr_g; /* 0x06 */
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u8 podr_h; /* 0x07 */
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u8 podr_i; /* 0x08 */
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u8 podr_j; /* 0x09 */
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u8 podr_k; /* 0x0A */
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u8 rsvd0; /* 0x0B */
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u8 pddr_a; /* 0x0C */
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u8 pddr_b; /* 0x0D */
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u8 pddr_c; /* 0x0E */
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u8 pddr_d; /* 0x0F */
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u8 pddr_e; /* 0x10 */
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u8 pddr_f; /* 0x11 */
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u8 pddr_g; /* 0x12 */
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u8 pddr_h; /* 0x13 */
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u8 pddr_i; /* 0x14 */
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u8 pddr_j; /* 0x15 */
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u8 pddr_k; /* 0x16 */
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u8 rsvd1; /* 0x17 */
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u8 ppdsdr_a; /* 0x18 */
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u8 ppdsdr_b; /* 0x19 */
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u8 ppdsdr_c; /* 0x1A */
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u8 ppdsdr_d; /* 0x1B */
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u8 ppdsdr_e; /* 0x1C */
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u8 ppdsdr_f; /* 0x1D */
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u8 ppdsdr_g; /* 0x1E */
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u8 ppdsdr_h; /* 0x1F */
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u8 ppdsdr_i; /* 0x20 */
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u8 ppdsdr_j; /* 0x21 */
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u8 ppdsdr_k; /* 0x22 */
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u8 rsvd2; /* 0x23 */
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u8 pclrr_a; /* 0x24 */
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u8 pclrr_b; /* 0x25 */
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u8 pclrr_c; /* 0x26 */
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u8 pclrr_d; /* 0x27 */
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u8 pclrr_e; /* 0x28 */
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u8 pclrr_f; /* 0x29 */
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u8 pclrr_g; /* 0x2A */
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u8 pclrr_h; /* 0x2B */
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u8 pclrr_i; /* 0x2C */
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u8 pclrr_j; /* 0x2D */
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u8 pclrr_k; /* 0x2E */
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u8 rsvd3; /* 0x2F */
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u16 pcr_a; /* 0x30 */
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u16 pcr_b; /* 0x32 */
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u16 pcr_c; /* 0x34 */
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u16 pcr_d; /* 0x36 */
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u16 pcr_e; /* 0x38 */
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u16 pcr_f; /* 0x3A */
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u16 pcr_g; /* 0x3C */
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u16 pcr_h; /* 0x3E */
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u16 pcr_i; /* 0x40 */
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u16 pcr_j; /* 0x42 */
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u16 pcr_k; /* 0x44 */
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u16 rsvd4; /* 0x46 */
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u8 par_fbctl; /* 0x48 */
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u8 par_be; /* 0x49 */
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u8 par_cs; /* 0x4A */
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u8 par_cani2c; /* 0x4B */
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u8 par_irqh; /* 0x4C */
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u8 par_irql; /* 0x4D */
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u8 par_dspi0; /* 0x4E */
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u8 par_dspiow; /* 0x4F */
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u8 par_timer; /* 0x50 */
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u8 par_uart2; /* 0x51 */
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u8 par_uart1; /* 0x52 */
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u8 par_uart0; /* 0x53 */
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u8 par_sdhch; /* 0x54 */
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u8 par_sdhcl; /* 0x55 */
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u8 par_simp0h; /* 0x56 */
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u8 par_simp1h; /* 0x57 */
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u8 par_ssi0h; /* 0x58 */
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u8 par_ssi0l; /* 0x59 */
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u8 par_dbg1h; /* 0x5A */
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u8 par_dbg0h; /* 0x5B */
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u8 par_dbgl; /* 0x5C */
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u8 rsvd5; /* 0x5D */
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u8 par_fec; /* 0x5E */
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u8 rsvd6; /* 0x5F */
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u8 mscr_sdram; /* 0x60 */
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u8 rsvd7[3]; /* 0x61-0x63 */
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u8 srcr_fb1; /* 0x64 */
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u8 srcr_fb2; /* 0x65 */
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u8 srcr_fb3; /* 0x66 */
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u8 srcr_fb4; /* 0x67 */
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u8 srcr_dspiow; /* 0x68 */
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u8 srcr_cani2c; /* 0x69 */
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u8 srcr_irq; /* 0x6A */
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u8 srcr_timer; /* 0x6B */
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u8 srcr_uart; /* 0x6C */
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u8 srcr_fec; /* 0x6D */
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u8 srcr_sdhc; /* 0x6E */
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u8 srcr_simp0; /* 0x6F */
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u8 srcr_ssi0; /* 0x70 */
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u8 rsvd8[3]; /* 0x71-0x73 */
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u16 urts_pol; /* 0x74 */
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u16 ucts_pol; /* 0x76 */
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u16 utxd_wom; /* 0x78 */
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u32 urxd_wom; /* 0x7c */
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u32 hcr1; /* 0x80 */
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u32 hcr0; /* 0x84 */
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} gpio_t;
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/* SDRAM Controller (SDRAMC) */
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typedef struct sdramc {
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u32 cr00; /* 0x00 */
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u32 cr01; /* 0x04 */
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u32 cr02; /* 0x08 */
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u32 cr03; /* 0x0C */
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u32 cr04; /* 0x10 */
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u32 cr05; /* 0x14 */
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u32 cr06; /* 0x18 */
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u32 cr07; /* 0x1C */
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u32 cr08; /* 0x20 */
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u32 cr09; /* 0x24 */
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u32 cr10; /* 0x28 */
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u32 cr11; /* 0x2C */
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u32 cr12; /* 0x30 */
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u32 cr13; /* 0x34 */
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u32 cr14; /* 0x38 */
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u32 cr15; /* 0x3C */
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u32 cr16; /* 0x40 */
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u32 cr17; /* 0x44 */
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u32 cr18; /* 0x48 */
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u32 cr19; /* 0x4C */
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u32 cr20; /* 0x50 */
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u32 cr21; /* 0x54 */
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u32 cr22; /* 0x58 */
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u32 cr23; /* 0x5C */
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u32 cr24; /* 0x60 */
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u32 cr25; /* 0x64 */
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u32 cr26; /* 0x68 */
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u32 cr27; /* 0x6C */
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u32 cr28; /* 0x70 */
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u32 cr29; /* 0x74 */
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u32 cr30; /* 0x78 */
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u32 cr31; /* 0x7C */
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u32 cr32; /* 0x80 */
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u32 cr33; /* 0x84 */
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u32 cr34; /* 0x88 */
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u32 cr35; /* 0x8C */
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u32 cr36; /* 0x90 */
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u32 cr37; /* 0x94 */
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u32 cr38; /* 0x98 */
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u32 cr39; /* 0x9C */
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u32 cr40; /* 0xA0 */
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u32 cr41; /* 0xA4 */
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u32 cr42; /* 0xA8 */
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u32 cr43; /* 0xAC */
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u32 cr44; /* 0xB0 */
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u32 cr45; /* 0xB4 */
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u32 cr46; /* 0xB8 */
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u32 cr47; /* 0xBC */
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u32 cr48; /* 0xC0 */
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u32 cr49; /* 0xC4 */
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u32 cr50; /* 0xC8 */
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u32 cr51; /* 0xCC */
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u32 cr52; /* 0xD0 */
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u32 cr53; /* 0xD4 */
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u32 cr54; /* 0xD8 */
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u32 cr55; /* 0xDC */
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u32 cr56; /* 0xE0 */
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u32 cr57; /* 0xE4 */
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u32 cr58; /* 0xE8 */
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u32 cr59; /* 0xEC */
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u32 cr60; /* 0xF0 */
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u32 cr61; /* 0xF4 */
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u32 cr62; /* 0xF8 */
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u32 cr63; /* 0xFC */
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u32 rsvd3[32]; /* 0xF4-0x1A8 */
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u32 rcrcr; /* 0x180 */
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u32 swrcr; /* 0x184 */
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u32 rcr; /* 0x188 */
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u32 msovr; /* 0x18C */
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u32 rcrdbg; /* 0x190 */
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u32 sl0adj; /* 0x194 */
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u32 sl1adj; /* 0x198 */
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u32 sl2adj; /* 0x19C */
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u32 sl3adj; /* 0x1A0 */
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u32 sl4adj; /* 0x1A4 */
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u32 flight_tm; /* 0x1A8 */
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u32 padcr; /* 0x1AC */
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} sdramc_t;
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/* Phase Locked Loop (PLL) */
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typedef struct pll {
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u32 pcr; /* Control */
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u32 pdr; /* Divider */
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u32 psr; /* Status */
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} pll_t;
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typedef struct scm {
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u8 rsvd1[19]; /* 0x00 - 0x12 */
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u8 wcr; /* 0x13 */
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u16 rsvd2; /* 0x14 - 0x15 */
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u16 cwcr; /* 0x16 */
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u8 rsvd3[3]; /* 0x18 - 0x1A */
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u8 cwsr; /* 0x1B */
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u8 rsvd4[3]; /* 0x1C - 0x1E */
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u8 scmisr; /* 0x1F */
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u32 rsvd5; /* 0x20 - 0x23 */
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u32 bcr; /* 0x24 */
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u8 rsvd6[72]; /* 0x28 - 0x6F */
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u32 cfadr; /* 0x70 */
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u8 rsvd7; /* 0x74 */
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u8 cfier; /* 0x75 */
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u8 cfloc; /* 0x76 */
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u8 cfatr; /* 0x77 */
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u32 rsvd8; /* 0x78 - 0x7B */
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u32 cfdtr; /* 0x7C */
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} scm_t;
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typedef struct pm {
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u8 pmsr0; /* */
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u8 pmcr0;
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u8 pmsr1;
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u8 pmcr1;
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u32 pmhr0;
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u32 pmlr0;
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u32 pmhr1;
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u32 pmlr1;
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} pm_t;
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#endif /* __IMMAP_5441X__ */
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