upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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127 lines
3.0 KiB
127 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* National Semiconductor DP83848 PHY Driver for TI DaVinci
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* (TMS320DM644x) based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* --------------------------------------------------------
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*/
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#include <common.h>
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#include <net.h>
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#include <dp83848.h>
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#include <asm/arch/emac_defs.h>
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#include "../../../drivers/net/davinci_emac.h"
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#ifdef CONFIG_DRIVER_TI_EMAC
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#ifdef CONFIG_CMD_NET
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int dp83848_is_phy_connected(int phy_addr)
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{
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u_int16_t id1, id2;
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if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
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return(0);
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if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
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return(0);
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if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
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return(1);
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return(0);
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}
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int dp83848_get_link_speed(int phy_addr)
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{
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u_int16_t tmp;
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volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
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if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
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return(0);
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if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
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return(0);
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if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
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return(0);
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/* Speed doesn't matter, there is no setting for it in EMAC... */
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if (tmp & DP83848_DUPLEX) {
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/* set DM644x EMAC for Full Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
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EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
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} else {
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/*set DM644x EMAC for Half Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
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}
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return(1);
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}
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int dp83848_init_phy(int phy_addr)
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{
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int ret = 1;
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if (!dp83848_get_link_speed(phy_addr)) {
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/* Try another time */
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udelay(100000);
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ret = dp83848_get_link_speed(phy_addr);
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}
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/* Disable PHY Interrupts */
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davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
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return(ret);
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}
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int dp83848_auto_negotiate(int phy_addr)
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{
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u_int16_t tmp;
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if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
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return(0);
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/* Restart Auto_negotiation */
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tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
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tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
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davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
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/* Set the Auto_negotiation Advertisement Register
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* MII advertising for Next page, 100BaseTxFD and HD,
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* 10BaseTFD and HD, IEEE 802.3
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*/
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tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
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DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
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davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
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/* Read Control Register */
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if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
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return(0);
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tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
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davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
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/* Restart Auto_negotiation */
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tmp |= DP83848_RESTART_AUTONEG;
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davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
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/*check AutoNegotiate complete */
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udelay(10000);
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if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
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return(0);
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if (!(tmp & DP83848_AUTONEG_COMP))
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return(0);
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return (dp83848_get_link_speed(phy_addr));
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* CONFIG_DRIVER_ETHER */
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