upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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110 lines
2.4 KiB
110 lines
2.4 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* EMIF programming
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*/
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#include <common.h>
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
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u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
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#endif
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#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
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static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
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.max_freq = 400000000,
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.RL = 6,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
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static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
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.max_freq = 200000000,
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.RL = 3,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 20,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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/*
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* Min tCK values specified by JESD209-2
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* Min tCK specifies the minimum duration of some AC timing parameters in terms
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* of the number of cycles. If the calculated number of cycles based on the
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* absolute time value is less than the min tCK value, min tCK value should
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* be used instead. This typically happens at low frequencies.
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*/
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static const struct lpddr2_min_tck min_tck_jedec = {
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.tRL = 3,
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.tRP_AB = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRAS_MIN = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
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&timings_jedec_200_mhz,
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&timings_jedec_400_mhz
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};
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const struct lpddr2_device_timings jedec_default_timings = {
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.ac_timings = jedec_ac_timings,
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.min_tck = &min_tck_jedec
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};
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void emif_get_device_timings(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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{
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/* Assume Identical devices on EMIF1 & EMIF2 */
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*cs0_device_timings = &jedec_default_timings;
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*cs1_device_timings = &jedec_default_timings;
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}
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#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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