upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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47 lines
1.3 KiB
47 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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* (c) Copyright 2016 Topic Embedded Products.
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*/
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#ifndef _ASM_ARCH_PS7_INIT_GPL_H
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#define _ASM_ARCH_PS7_INIT_GPL_H
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/* Opcode exit is 0 all the time */
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#define OPCODE_EXIT 0U
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#define OPCODE_MASKWRITE 0U
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#define OPCODE_MASKPOLL 1U
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#define OPCODE_MASKDELAY 2U
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#define OPCODE_WRITE 3U
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#define OPCODE_ADDRESS_MASK (~3U)
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/* Sentinel */
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#define EMIT_EXIT() OPCODE_EXIT
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/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
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#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
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#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
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#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
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#define EMIT_WRITE(addr, val) OPCODE_WRITE | addr, val
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/* Returns codes of ps7_init* */
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#define PS7_INIT_SUCCESS (0)
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#define PS7_INIT_CORRUPT (1)
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#define PS7_INIT_TIMEOUT (2)
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#define PS7_POLL_FAILED_DDR_INIT (3)
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#define PS7_POLL_FAILED_DMA (4)
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#define PS7_POLL_FAILED_PLL (5)
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#define PCW_SILICON_VERSION_1 0
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#define PCW_SILICON_VERSION_2 1
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#define PCW_SILICON_VERSION_3 2
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/* Called by spl.c */
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int ps7_init(void);
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int ps7_post_config(void);
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/* Defined in ps7_init_common.c */
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int ps7_config(unsigned long *ps7_config_init);
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unsigned long ps7GetSiliconVersion(void);
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#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
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