upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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34 lines
1.1 KiB
34 lines
1.1 KiB
/*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "clk-uniphier.h"
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const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = {
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UNIPHIER_CLK_GATE(8, 0x2104, 10), /* stdmac */
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UNIPHIER_CLK_GATE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
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UNIPHIER_CLK_GATE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
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UNIPHIER_CLK_GATE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
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UNIPHIER_CLK_GATE(16, 0x2104, 19), /* usb30-phy (PXs2) */
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UNIPHIER_CLK_GATE(20, 0x2104, 20), /* usb31-phy (PXs2) */
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UNIPHIER_CLK_END
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};
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const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = {
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.gate = uniphier_pxs2_sys_clk_gate,
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};
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const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = {
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UNIPHIER_CLK_GATE(8, 0x210c, 8), /* stdmac */
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UNIPHIER_CLK_GATE(14, 0x210c, 14), /* usb30 (LD20) */
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UNIPHIER_CLK_GATE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
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UNIPHIER_CLK_GATE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
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UNIPHIER_CLK_END
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};
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const struct uniphier_clk_data uniphier_ld20_sys_clk_data = {
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.gate = uniphier_ld20_sys_clk_gate,
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};
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