upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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143 lines
3.0 KiB
143 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx PCS/PMA Core phy driver
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*
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* Copyright (C) 2015 - 2016 Xilinx, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MII_PHY_STATUS_SPD_MASK 0x0C00
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#define MII_PHY_STATUS_FULLDUPLEX 0x1000
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#define MII_PHY_STATUS_1000 0x0800
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#define MII_PHY_STATUS_100 0x0400
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#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF
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/* Mask used for ID comparisons */
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#define XILINX_PHY_ID_MASK 0xfffffff0
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/* Known PHY IDs */
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#define XILINX_PHY_ID 0x01740c00
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/* struct phy_device dev_flags definitions */
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#define XAE_PHY_TYPE_MII 0
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#define XAE_PHY_TYPE_GMII 1
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#define XAE_PHY_TYPE_RGMII_1_3 2
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#define XAE_PHY_TYPE_RGMII_2_0 3
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#define XAE_PHY_TYPE_SGMII 4
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#define XAE_PHY_TYPE_1000BASE_X 5
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static int xilinxphy_startup(struct phy_device *phydev)
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{
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int err;
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int status = 0;
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debug("%s\n", __func__);
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/* Update the link, but return if there
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* was an error
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*/
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err = genphy_update_link(phydev);
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if (err)
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return err;
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if (AUTONEG_ENABLE == phydev->autoneg) {
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status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
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status = status & MII_PHY_STATUS_SPD_MASK;
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if (status & MII_PHY_STATUS_FULLDUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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switch (status) {
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case MII_PHY_STATUS_1000:
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phydev->speed = SPEED_1000;
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break;
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case MII_PHY_STATUS_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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} else {
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int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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if (bmcr & BMCR_FULLDPLX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (bmcr & BMCR_SPEED1000)
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phydev->speed = SPEED_1000;
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else if (bmcr & BMCR_SPEED100)
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phydev->speed = SPEED_100;
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else
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phydev->speed = SPEED_10;
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}
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/*
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* For 1000BASE-X Phy Mode the speed/duplex will always be
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* 1000Mbps/fullduplex
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*/
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if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) {
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_1000;
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}
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return 0;
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}
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static int xilinxphy_of_init(struct phy_device *phydev)
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{
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u32 phytype;
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debug("%s\n", __func__);
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phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
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"xlnx,phy-type", -1);
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if (phytype == XAE_PHY_TYPE_1000BASE_X)
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phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
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return 0;
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}
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static int xilinxphy_config(struct phy_device *phydev)
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{
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int temp;
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debug("%s\n", __func__);
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xilinxphy_of_init(phydev);
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temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp);
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return 0;
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}
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static struct phy_driver xilinxphy_driver = {
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.uid = XILINX_PHY_ID,
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.mask = XILINX_PHY_ID_MASK,
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.name = "Xilinx PCS/PMA PHY",
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.features = PHY_GBIT_FEATURES,
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.config = &xilinxphy_config,
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.startup = &xilinxphy_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_xilinx_init(void)
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{
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debug("%s\n", __func__);
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phy_register(&xilinxphy_driver);
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return 0;
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}
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