upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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147 lines
2.9 KiB
147 lines
2.9 KiB
/*
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* (C) Copyright 2007
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* Stefano Babic, DENX Gmbh, sbabic@denx.de
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*
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* (C) Copyright 2004
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* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa.h>
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#include <asm/arch/regs-mmc.h>
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#include <netdev.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define RH_A_PSM (1 << 8) /* power switching mode */
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#define RH_A_NPS (1 << 9) /* no power switching */
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extern struct serial_device serial_ffuart_device;
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extern struct serial_device serial_btuart_device;
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extern struct serial_device serial_stuart_device;
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#if CONFIG_MK_POLARIS
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#define BOOT_CONSOLE "serial_stuart"
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#else
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#define BOOT_CONSOLE "serial_ffuart"
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int usb_board_init(void)
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{
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writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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;
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
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writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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return 0;
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}
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void usb_board_init_fail(void)
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{
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return;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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int board_init (void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of ConXS Board */
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gd->bd->bi_arch_number = 776;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa000003c;
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return 0;
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}
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int board_late_init(void)
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{
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char *console=getenv("boot_console");
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if ((console == NULL) || (strcmp(console,"serial_btuart") &&
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strcmp(console,"serial_stuart") &&
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strcmp(console,"serial_ffuart"))) {
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console = BOOT_CONSOLE;
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}
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setenv("stdout",console);
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setenv("stdin", console);
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setenv("stderr",console);
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bis)
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{
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pxa_mmc_register(0);
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return 0;
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}
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#endif
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