upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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550 lines
15 KiB
550 lines
15 KiB
/*
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* board.c
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*
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* Board functions for TI AM335X based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define MII_MODE_ENABLE 0x0
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#define RGMII_MODE_ENABLE 0x3A
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static struct am335x_baseboard_id __attribute__((section (".data"))) header;
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static inline int board_is_bone(void)
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{
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return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
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}
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static inline int board_is_bone_lt(void)
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{
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return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
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}
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static inline int board_is_evm_sk(void)
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{
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return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
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}
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static inline int board_is_idk(void)
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{
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return !strncmp(header.config, "SKU#02", 6);
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}
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static int __maybe_unused board_is_gp_evm(void)
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{
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return !strncmp("A33515BB", header.name, 8);
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}
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int board_is_evm_15_or_later(void)
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{
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return (!strncmp("A33515BB", header.name, 8) &&
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strncmp("1.5", header.version, 3) <= 0);
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}
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(void)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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puts("Could not probe the EEPROM; something fundamentally "
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"wrong on the I2C bus.\n");
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
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sizeof(header))) {
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puts("Could not read the EEPROM; something fundamentally"
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" wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header.magic != 0xEE3355AA) {
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/*
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* read the eeprom using i2c again,
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* but use only a 1 byte address
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*/
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
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(uchar *)&header, sizeof(header))) {
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puts("Could not read the EEPROM; something "
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"fundamentally wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header.magic != 0xEE3355AA) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header.magic);
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return -EINVAL;
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}
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}
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return 0;
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}
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
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(MT47H128M16RT25E_RD_DQS<<20) |
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(MT47H128M16RT25E_RD_DQS<<10) |
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(MT47H128M16RT25E_RD_DQS<<0)),
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.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
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(MT47H128M16RT25E_WR_DQS<<20) |
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(MT47H128M16RT25E_WR_DQS<<10) |
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(MT47H128M16RT25E_WR_DQS<<0)),
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.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
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(MT47H128M16RT25E_PHY_WRLVL<<20) |
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(MT47H128M16RT25E_PHY_WRLVL<<10) |
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(MT47H128M16RT25E_PHY_WRLVL<<0)),
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.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
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(MT47H128M16RT25E_PHY_GATELVL<<20) |
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(MT47H128M16RT25E_PHY_GATELVL<<10) |
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(MT47H128M16RT25E_PHY_GATELVL<<0)),
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.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
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.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
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(MT47H128M16RT25E_PHY_WR_DATA<<20) |
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(MT47H128M16RT25E_PHY_WR_DATA<<10) |
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(MT47H128M16RT25E_PHY_WR_DATA<<0)),
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.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr2_cmd_ctrl_data = {
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.cmd0csratio = MT47H128M16RT25E_RATIO,
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.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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.cmd1csratio = MT47H128M16RT25E_RATIO,
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.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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.cmd2csratio = MT47H128M16RT25E_RATIO,
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.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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};
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static const struct emif_regs ddr2_emif_reg_data = {
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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};
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J128MJT125_RD_DQS,
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.datawdsratio0 = MT41J128MJT125_WR_DQS,
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.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
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.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct ddr_data ddr3_beagleblack_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct ddr_data ddr3_evm_data = {
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.datardsratio0 = MT41J512M8RH125_RD_DQS,
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.datawdsratio0 = MT41J512M8RH125_WR_DQS,
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.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
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.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41J128MJT125_RATIO,
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.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd1csratio = MT41J128MJT125_RATIO,
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.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd2csratio = MT41J128MJT125_RATIO,
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.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
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};
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static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
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.cmd0csratio = MT41J512M8RH125_RATIO,
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.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
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.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
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.cmd1csratio = MT41J512M8RH125_RATIO,
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.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
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.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
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.cmd2csratio = MT41J512M8RH125_RATIO,
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.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
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.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41J128MJT125_EMIF_SDCFG,
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.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
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.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
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.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
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.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
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.zq_config = MT41J128MJT125_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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static struct emif_regs ddr3_beagleblack_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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static struct emif_regs ddr3_evm_emif_reg_data = {
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.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
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.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
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.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
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.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
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.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
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.zq_config = MT41J512M8RH125_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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#endif
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/*
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* early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regVal;
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#ifdef CONFIG_SERIAL1
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enable_uart0_pin_mux();
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#endif /* CONFIG_SERIAL1 */
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#ifdef CONFIG_SERIAL2
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enable_uart1_pin_mux();
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#endif /* CONFIG_SERIAL2 */
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#ifdef CONFIG_SERIAL3
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enable_uart2_pin_mux();
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#endif /* CONFIG_SERIAL3 */
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#ifdef CONFIG_SERIAL4
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enable_uart3_pin_mux();
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#endif /* CONFIG_SERIAL4 */
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#ifdef CONFIG_SERIAL5
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enable_uart4_pin_mux();
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#endif /* CONFIG_SERIAL5 */
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#ifdef CONFIG_SERIAL6
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enable_uart5_pin_mux();
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#endif /* CONFIG_SERIAL6 */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_RESET;
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writel(regVal, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_SMART_IDLE_EN;
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writel(regVal, &uart_base->uartsyscfg);
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gd = &gdata;
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preloader_console_init();
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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enable_board_pin_mux(&header);
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if (board_is_evm_sk()) {
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/*
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* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
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* This is safe enough to do on older revs.
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*/
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gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
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gpio_direction_output(GPIO_DDR_VTT_EN, 1);
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}
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if (board_is_evm_sk())
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config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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else if (board_is_bone_lt())
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config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
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&ddr3_beagleblack_data,
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&ddr3_beagleblack_cmd_ctrl_data,
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&ddr3_beagleblack_emif_reg_data, 0);
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else if (board_is_evm_15_or_later())
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config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
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&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
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else
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config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
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#endif
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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char safe_string[HDR_NAME_LEN + 1];
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|
|
/* Now set variables based on the header. */
|
|
strncpy(safe_string, (char *)header.name, sizeof(header.name));
|
|
safe_string[sizeof(header.name)] = 0;
|
|
setenv("board_name", safe_string);
|
|
|
|
strncpy(safe_string, (char *)header.version, sizeof(header.version));
|
|
safe_string[sizeof(header.version)] = 0;
|
|
setenv("board_rev", safe_string);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
|
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
|
static void cpsw_control(int enabled)
|
|
{
|
|
/* VTP can be added here */
|
|
|
|
return;
|
|
}
|
|
|
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
|
{
|
|
.slave_reg_ofs = 0x208,
|
|
.sliver_reg_ofs = 0xd80,
|
|
.phy_id = 0,
|
|
},
|
|
{
|
|
.slave_reg_ofs = 0x308,
|
|
.sliver_reg_ofs = 0xdc0,
|
|
.phy_id = 1,
|
|
},
|
|
};
|
|
|
|
static struct cpsw_platform_data cpsw_data = {
|
|
.mdio_base = CPSW_MDIO_BASE,
|
|
.cpsw_base = CPSW_BASE,
|
|
.mdio_div = 0xff,
|
|
.channels = 8,
|
|
.cpdma_reg_ofs = 0x800,
|
|
.slaves = 1,
|
|
.slave_data = cpsw_slaves,
|
|
.ale_reg_ofs = 0xd00,
|
|
.ale_entries = 1024,
|
|
.host_port_reg_ofs = 0x108,
|
|
.hw_stats_reg_ofs = 0x900,
|
|
.mac_control = (1 << 5),
|
|
.control = cpsw_control,
|
|
.host_port_num = 0,
|
|
.version = CPSW_CTRL_VERSION_2,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_DRIVER_TI_CPSW) || \
|
|
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int rv, n = 0;
|
|
uint8_t mac_addr[6];
|
|
uint32_t mac_hi, mac_lo;
|
|
|
|
/* try reading mac address from efuse */
|
|
mac_lo = readl(&cdev->macid0l);
|
|
mac_hi = readl(&cdev->macid0h);
|
|
mac_addr[0] = mac_hi & 0xFF;
|
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
|
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
|
mac_addr[4] = mac_lo & 0xFF;
|
|
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
|
|
|
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
|
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
|
if (!getenv("ethaddr")) {
|
|
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
|
|
|
if (is_valid_ether_addr(mac_addr))
|
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
|
}
|
|
|
|
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
|
|
writel(MII_MODE_ENABLE, &cdev->miisel);
|
|
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
|
PHY_INTERFACE_MODE_MII;
|
|
} else {
|
|
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
|
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
|
PHY_INTERFACE_MODE_RGMII;
|
|
}
|
|
|
|
rv = cpsw_register(&cpsw_data);
|
|
if (rv < 0)
|
|
printf("Error %d registering CPSW switch\n", rv);
|
|
else
|
|
n += rv;
|
|
|
|
/*
|
|
*
|
|
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
|
* operating points. So we must set the TX clock delay feature
|
|
* in the AR8051 PHY. Since we only support a single ethernet
|
|
* device in U-Boot, we only do this for the first instance.
|
|
*/
|
|
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
|
|
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
|
|
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
|
|
#define AR8051_RGMII_TX_CLK_DLY 0x100
|
|
|
|
if (board_is_evm_sk() || board_is_gp_evm()) {
|
|
const char *devname;
|
|
devname = miiphy_get_current_dev();
|
|
|
|
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
|
|
AR8051_DEBUG_RGMII_CLK_DLY_REG);
|
|
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
|
|
AR8051_RGMII_TX_CLK_DLY);
|
|
}
|
|
#endif
|
|
#if defined(CONFIG_USB_ETHER) && \
|
|
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
|
|
if (is_valid_ether_addr(mac_addr))
|
|
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
|
|
|
|
rv = usb_eth_initialize(bis);
|
|
if (rv < 0)
|
|
printf("Error %d registering USB_ETHER\n", rv);
|
|
else
|
|
n += rv;
|
|
#endif
|
|
return n;
|
|
}
|
|
#endif
|
|
|