upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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273 lines
6.2 KiB
273 lines
6.2 KiB
/*
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* evm.c
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*
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* Board functions for TI814x EVM
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <cpsw.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include "evm.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* UART Defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static void uart_enable(void)
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{
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u32 regVal;
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/* UART softreset */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_RESET;
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writel(regVal, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_SMART_IDLE_EN;
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writel(regVal, &uart_base->uartsyscfg);
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}
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static void wdt_disable(void)
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{
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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}
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static const struct cmd_control evm_ddr2_cctrl_data = {
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.cmd0csratio = 0x80,
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.cmd0dldiff = 0x04,
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.cmd0iclkout = 0x00,
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.cmd1csratio = 0x80,
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.cmd1dldiff = 0x04,
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.cmd1iclkout = 0x00,
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.cmd2csratio = 0x80,
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.cmd2dldiff = 0x04,
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.cmd2iclkout = 0x00,
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};
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static const struct emif_regs evm_ddr2_emif0_regs = {
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.sdram_config = 0x40801ab2,
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.ref_ctrl = 0x10000c30,
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.sdram_tim1 = 0x0aaaf552,
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.sdram_tim2 = 0x043631d2,
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.sdram_tim3 = 0x00000327,
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.emif_ddr_phy_ctlr_1 = 0x00000007
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};
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static const struct emif_regs evm_ddr2_emif1_regs = {
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.sdram_config = 0x40801ab2,
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.ref_ctrl = 0x10000c30,
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.sdram_tim1 = 0x0aaaf552,
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.sdram_tim2 = 0x043631d2,
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.sdram_tim3 = 0x00000327,
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.emif_ddr_phy_ctlr_1 = 0x00000007
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};
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const struct dmm_lisa_map_regs evm_lisa_map_regs = {
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.dmm_lisa_map_0 = 0x00000000,
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.dmm_lisa_map_1 = 0x00000000,
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.dmm_lisa_map_2 = 0x806c0300,
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.dmm_lisa_map_3 = 0x806c0300,
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};
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static const struct ddr_data evm_ddr2_data = {
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.datardsratio0 = ((0x35<<10) | (0x35<<0)),
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.datawdsratio0 = ((0x20<<10) | (0x20<<0)),
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.datawiratio0 = ((0<<10) | (0<<0)),
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.datagiratio0 = ((0<<10) | (0<<0)),
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.datafwsratio0 = ((0x90<<10) | (0x90<<0)),
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.datawrsratio0 = ((0x50<<10) | (0x50<<0)),
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.datauserank0delay = 1,
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.datadldiff0 = 0x4,
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};
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#endif
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/*
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* early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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wdt_disable();
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/* Enable timer */
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timer_init();
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* Set UART pins */
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enable_uart0_pin_mux();
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/* Set MMC pins */
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enable_mmc1_pin_mux();
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/* Set Ethernet pins */
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enable_enet_pin_mux();
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/* Enable UART */
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uart_enable();
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gd = &gdata;
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preloader_console_init();
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config_dmm(&evm_lisa_map_regs);
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config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
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&evm_ddr2_emif0_regs, 0);
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config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
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&evm_ddr2_emif1_regs, 1);
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#endif
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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return 0;
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}
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(1, 0, 0, -1, -1);
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return 0;
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x50,
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.sliver_reg_ofs = 0x700,
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.phy_id = 1,
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},
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{
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.slave_reg_ofs = 0x90,
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.sliver_reg_ofs = 0x740,
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.phy_id = 0,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x100,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0x600,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x28,
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.hw_stats_reg_ofs = 0x400,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_1,
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};
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#endif
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int board_eth_init(bd_t *bis)
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{
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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printf("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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else
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printf("Unable to read MAC address. Set <ethaddr>\n");
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}
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return cpsw_register(&cpsw_data);
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}
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