upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
2.1 KiB
78 lines
2.1 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <nand.h>
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static void at91_nand_hwcontrol(struct mtd_info *mtd,
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int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
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| CONFIG_SYS_NAND_MASK_CLE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
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at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
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!(ctrl & NAND_NCE));
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SYS_NAND_READY_PIN
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static int at91_nand_ready(struct mtd_info *mtd)
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{
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return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
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}
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#endif
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int board_nand_init(struct nand_chip *nand)
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{
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nand->ecc.mode = NAND_ECC_SOFT;
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#ifdef CONFIG_SYS_NAND_DBW_16
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nand->options = NAND_BUSWIDTH_16;
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#endif
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nand->cmd_ctrl = at91_nand_hwcontrol;
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#ifdef CONFIG_SYS_NAND_READY_PIN
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nand->dev_ready = at91_nand_ready;
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#endif
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nand->chip_delay = 20;
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return 0;
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}
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