upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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242 lines
7.4 KiB
242 lines
7.4 KiB
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/pirq_routing.h>
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#include <asm/arch/device.h>
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#include <asm/arch/tnc.h>
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#include <asm/arch/irq.h>
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static struct irq_routing_table *pirq_routing_table;
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bool pirq_check_irq_routed(int link, u8 irq)
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{
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u8 pirq;
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pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
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pirq &= 0xf;
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/* IRQ# 0/1/2/8/13 are reserved */
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if (pirq < 3 || pirq == 8 || pirq == 13)
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return false;
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return pirq == irq ? true : false;
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}
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int pirq_translate_link(int link)
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{
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return LINK_V2N(link);
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}
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void pirq_assign_irq(int link, u8 irq)
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{
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/* IRQ# 0/1/2/8/13 are reserved */
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if (irq < 3 || irq == 8 || irq == 13)
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return;
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x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
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}
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static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
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u8 device, u8 func, u8 pin, u8 pirq)
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{
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struct irq_info *slot = *slotp;
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slot->bus = bus;
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slot->devfn = (device << 3) | func;
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slot->irq[pin - 1].link = LINK_N2V(pirq);
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slot->irq[pin - 1].bitmap = PIRQ_BITMAP;
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(*entries)++;
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(*slotp)++;
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}
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/* PCIe port downstream INTx swizzle */
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static inline u8 pin_swizzle(u8 pin, int port)
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{
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return (pin + port) % 4;
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}
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__weak int board_fill_irq_info(struct irq_info *slot)
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{
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return 0;
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}
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static int create_pirq_routing_table(void)
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{
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struct irq_routing_table *rt;
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struct irq_info *slot;
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int irq_entries = 0;
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pci_dev_t tcf_bdf;
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u8 tcf_bus, bus;
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int i;
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rt = malloc(sizeof(struct irq_routing_table));
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if (!rt)
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return -ENOMEM;
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memset((char *)rt, 0, sizeof(struct irq_routing_table));
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/* Populate the PIRQ table fields */
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rt->signature = PIRQ_SIGNATURE;
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rt->version = PIRQ_VERSION;
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rt->rtr_bus = 0;
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rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC;
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rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
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rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
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slot = rt->slots;
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/*
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* Now fill in the irq_info entries in the PIRQ table
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*
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* We start from internal TunnelCreek PCI devices first, then
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* followed by all the 4 PCIe ports downstream devices, including
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* the Queensbay platform Topcliff chipset devices.
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*/
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fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV,
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TNC_IGD_FUNC, INTA, PIRQE);
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fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV,
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TNC_SDVO_FUNC, INTA, PIRQF);
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fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV,
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TNC_HDA_FUNC, INTA, PIRQG);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV,
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TNC_PCIE0_FUNC, INTA, PIRQE);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV,
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TNC_PCIE1_FUNC, INTA, PIRQF);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV,
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TNC_PCIE2_FUNC, INTA, PIRQG);
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fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV,
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TNC_PCIE3_FUNC, INTA, PIRQH);
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/* Check which PCIe port the Topcliff chipset is connected to */
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tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0);
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tcf_bus = PCI_BUS(tcf_bdf);
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for (i = 0; i < 4; i++) {
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bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0),
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PCI_SECONDARY_BUS);
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if (bus == tcf_bus)
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break;
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}
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/* Fill in the Topcliff chipset devices' irq info */
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if (i < 4) {
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV,
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TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i));
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tcf_bus++;
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
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TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
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TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
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TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
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TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
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TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6,
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TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
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TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
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TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i));
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fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
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TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i));
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}
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/* Call board-specific routine to fill in add-in card's irq info */
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irq_entries += board_fill_irq_info(slot);
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rt->size = irq_entries * sizeof(struct irq_info) + 32;
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pirq_routing_table = rt;
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return 0;
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}
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void pirq_init(void)
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{
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struct tnc_rcba *rcba;
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u32 base;
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base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
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base &= ~MEM_BAR_EN;
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rcba = (struct tnc_rcba *)base;
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/* Make sure all internal PCI devices are using INTA */
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writel(INTA, &rcba->d02ip);
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writel(INTA, &rcba->d03ip);
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writel(INTA, &rcba->d27ip);
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writel(INTA, &rcba->d31ip);
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writel(INTA, &rcba->d23ip);
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writel(INTA, &rcba->d24ip);
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writel(INTA, &rcba->d25ip);
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writel(INTA, &rcba->d26ip);
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/*
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* Route TunnelCreek PCI device interrupt pin to PIRQ
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*
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* Since PCIe downstream ports received INTx are routed to PIRQ
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* A/B/C/D directly and not configurable, we route internal PCI
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* device's INTx to PIRQ E/F/G/H.
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*/
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writew(PIRQE, &rcba->d02ir);
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writew(PIRQF, &rcba->d03ir);
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writew(PIRQG, &rcba->d27ir);
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writew(PIRQH, &rcba->d31ir);
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writew(PIRQE, &rcba->d23ir);
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writew(PIRQF, &rcba->d24ir);
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writew(PIRQG, &rcba->d25ir);
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writew(PIRQH, &rcba->d26ir);
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if (create_pirq_routing_table()) {
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debug("Failed to create pirq routing table\n");
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} else {
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/* Route PIRQ */
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pirq_route_irqs(pirq_routing_table->slots,
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get_irq_slot_count(pirq_routing_table));
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}
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}
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u32 write_pirq_routing_table(u32 addr)
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{
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return copy_pirq_routing_table(addr, pirq_routing_table);
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}
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