upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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52 lines
1.7 KiB
52 lines
1.7 KiB
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/gpio.h>
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/*
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* Routine: gpio_config_uart
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* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
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*/
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void gpio_config_uart(void)
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{
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int gp = GPIO_PI3;
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struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)];
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u32 val;
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/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
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val = readl(&bank->gpio_config[GPIO_PORT(gp)]);
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val |= 1 << GPIO_BIT(gp);
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writel(val, &bank->gpio_config[GPIO_PORT(gp)]);
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val = readl(&bank->gpio_out[GPIO_PORT(gp)]);
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val &= ~(1 << GPIO_BIT(gp));
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writel(val, &bank->gpio_out[GPIO_PORT(gp)]);
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val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]);
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val |= 1 << GPIO_BIT(gp);
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writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
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}
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