upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
1.3 KiB
60 lines
1.3 KiB
config ARCH_LS1012A
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bool
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select FSL_LSCH2
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315
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config ARCH_LS1043A
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bool
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select FSL_LSCH2
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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config ARCH_LS1046A
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bool
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select FSL_LSCH2
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select SYS_FSL_ERRATUM_A010539
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config ARCH_LS2080A
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bool
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select FSL_LSCH3
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config FSL_LSCH2
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bool
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config FSL_LSCH3
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bool
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config SYS_FSL_MMDC
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bool
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for Layerscape"
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A
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endmenu
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