upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/arc/include/asm/cache.h

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/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
#include <config.h>
/*
* The current upper bound for ARC L1 data cache line sizes is 128 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 128
#endif
#endif /* __ASM_ARC_CACHE_H */